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BCM4330FKUBG 参数 Datasheet PDF下载

BCM4330FKUBG图片预览
型号: BCM4330FKUBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Telecom Circuit, 1-Func, PBGA133, WLBGA-133]
分类和应用:
文件页数/大小: 168 页 / 1861 K
品牌: CYPRESS [ CYPRESS ]
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BCM4330 Preliminary Data Sheet  
GPIO Interface  
GPIO Interface  
There are seven general purpose I/O (GPIO) pins available on the WLAN section of the BCM4330 that can be  
used to connect to various external devices.  
Upon power up and reset, these pins become tri-stated. Subsequently, they can be programmed to be either  
input or output pins via the GPIO control register. An internal pull-up resistor is included on each GPIO. If a GPIO  
output enable is not asserted, and the corresponding GPIO signal is not being driven externally, the GPIO is  
read as high.  
External Coexistence Interface  
An external handshake interface is available to enable signaling between the device and an external co-located  
wireless device, such as GPS, WiMax, or UWB, to manage wireless medium sharing for optimum performance.  
The following signals can be enabled by software on the indicated WL_GPIO pins:  
• ERCX_STATUS—WL_GPIO1  
• ERCX_FREQ—WL_GPIO2  
• ERCX_RF_ACTIVE—WL_GPIO3  
• ERCX_TXCONF—WL_GPIO4  
• ERCX_PRISEL—WL_GPIO5  
UART Interface  
One UART interface can be enabled by software as an alternate function on pins WL_GPIO4 and WL_GPIO_3.  
Provided primarily for debugging during development, this UART enables the BCM4330 to operate as RS-232  
data termination equipment (DTE) for exchanging and managing data with other serial devices. It is compatible  
with the industry standard 16550 UART, and it provides a FIFO size of 64 × 8 in each direction.  
JTAG Interface  
The BCM4330 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB  
assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist customers by  
using proprietary debug and characterization test tools during board bringup. Therefore, it is highly  
recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs.  
Caution! The BCM4330 I/O interface pins are not 3.3V tolerant. All I/O signaling should be limited to  
2.9V ±3%, 2.5V, 1.8V, or 1.2V, depending on the I/O power supply voltage VDDIO. This applies to the  
GPIO, External Coexistence, UART, and JTAG signals.  
®
BROADCOM  
BCM4330 Preliminary Data Sheet  
April 28, 2011 • 4330-DS304-RI  
Page 73  
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