欢迎访问ic37.com |
会员登录 免费注册
发布采购

BCM4330FKUBG 参数 Datasheet PDF下载

BCM4330FKUBG图片预览
型号: BCM4330FKUBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Telecom Circuit, 1-Func, PBGA133, WLBGA-133]
分类和应用:
文件页数/大小: 168 页 / 1861 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号BCM4330FKUBG的Datasheet PDF文件第68页浏览型号BCM4330FKUBG的Datasheet PDF文件第69页浏览型号BCM4330FKUBG的Datasheet PDF文件第70页浏览型号BCM4330FKUBG的Datasheet PDF文件第71页浏览型号BCM4330FKUBG的Datasheet PDF文件第73页浏览型号BCM4330FKUBG的Datasheet PDF文件第74页浏览型号BCM4330FKUBG的Datasheet PDF文件第75页浏览型号BCM4330FKUBG的Datasheet PDF文件第76页  
BCM4330 Preliminary Data Sheet  
WLAN Global Functions  
Section 10: WLAN Global Functions  
WLAN CPU and Memory Subsystem  
The BCM4330 includes an integrated ARM Cortex-M3™ processor with internal RAM and ROM. The ARM  
Cortex-M3 processor is a low-power processor that features low gate count, low interrupt latency, and low-cost  
debug. It is intended for deeply embedded applications that require fast interrupt response features. The  
processor implements the ARM architecture v7-M with support for Thumb®-2 instruction set. ARM Cortex-M3  
delivers 30% more performance gain over ARM7TDMI.  
At 0.19uW/MHz, the Cortex-M3 is the most power efficient general purpose microprocessor available,  
outperforming 8- and 16-bit devices on MIPS/uW. It supports integrated sleep modes.  
ARM Cortex-M3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin  
overhead, and reduced silicon area. ARM Cortex-M3 supports independent buses for Code and Data access  
(ICode/DCode and System buses). ARM Cortex-M3 supports extensive debug features including real time trace  
of program execution.  
On-chip memory for the CPU includes 288 KB SRAM and 512 KB ROM.  
One-Time-Programmable Memory  
Various hardware configuration parameters may be stored in an internal 2 Kbit one-time-programmable (OTP)  
memory, which is read by system software after device reset. In addition, customer-specific parameters,  
including the system vendor ID and the MAC address can be stored, depending on the specific board design.  
The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot  
be reprogrammed to 0. The entire OTP array can be programmed in a single write cycle using a utility provided  
with the Broadcom WLAN manufacturing test tools. Alternatively, multiple write cycles can be used to  
selectively program specific bytes, but only bits which are still in the 0 state can be altered during each  
programming cycle.  
Prior to OTP programming, all values should be verified using the appropriate editable nvram.txt file, which is  
provided with the reference board design package. Documentation on the OTP development process is  
available on the Broadcom customer support portal (http://www.broadcom.com/support).  
®
BROADCOM  
BCM4330 Preliminary Data Sheet  
April 28, 2011 • 4330-DS304-RI  
Page 72  
 复制成功!