BCM4325
Preliminary Data Sheet
6/30/09
Normally, the UART baud rate is set by a configuration record downloaded after reset or automatic baud rate detection and
the host does not need to adjust the baud rate. Support for changing the baud rate during normal HCI UART operation is
provided through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The
BCM4325 UART operates correctly with the host UART, if the combined baud rate error of the two devices is within 5%.
AUTO-BAUDRATE DETECTION
The BCM4325 may be put into a state where it attempts to automatically detect the baud rate. This is done by holding the
BT_UART_CTS_N signal low during reset or power up. An auto-baud character A (0x41) or the HCI_RESET command
{0x01, 0x03, 0x0C, 0x00} can be sent from the host to train the BCM4325 UART when this feature is used.
The corresponding successful returns from BCM4325 auto-baud response are:
{0x41, 0x30, 0x34, 0x31} for the autobaud character
{0x04, 0x0E, 0x04, 0x01, 0x03, 0x0C, 0x00, 0x34, 0x31} for the HCI_RESET command
The run-time configuration download through the vendor specified commands is required to further configure the BCM4325
for normal operations. The BCM4325 can automatically detect baud rates up to the external crystal frequency divided by 16.
I2S INTERFACE
The 3-wire I2S interface for FM audio supports both master and slave modes. Input reference clock frequencies of 13 MHz,
19.2 MHz, 26 MHz, and 38.4 MHz are supported.
The three I2S signals are:
I2S Clock:
I2S Word Select: I2S_WS
I2S Data Out:
I2S_SDO
I2S_SCK
I2S_SCK and I2S_WS become outputs in Master mode and inputs in Slave mode, while I2S_SDO always stays as an
output. I2S data input is not supported. The channel word length is 16 bits and the data is justified so that the MSB of the left
channel data is aligned with the MSB of the I2S bus, per the I2S specification. The MSB of each data word is transmitted one
bit clock cycle after the I2S_WS transition, synchronous with the falling edge of bit clock. Left channel data is transmitted
when I2S_WS is low, and right channel data is transmitted when I2S_WS is high. Data bits sent by the BCM4325 are
synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK.
The clock rate in master mode is either of the following:
48 kHz x 32 bits per frame = 1.536 MHz
48 kHz x 50 bits per frame = 2.400 MHz
The master clock is generated from the input reference clock using a N/M clock divider. In Slave mode, any clock rate is
supported to a maximum of 3.072 MHz.
The I2S_SCK interface is available as multiplexed signals onto:
•
•
PCM interface
Class 1 control signals
Broadcom Corporation
Page 22
I2S Interface
Document 4325-DS04-R
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