Preliminary Data Sheet
6/30/09
BCM4325
In order to support both high and low baud rates efficiently, the UART clock can be selected as either 24 or 48 MHz.
Generally, the higher speed clock is needed for baud rates over 3 Mbaud, however a lower speed clock may be used to
achieve a more accurate baud rate under 3 Mbaud. The baud rate of the BCM4325 UART is controlled by two values. The
first is a UART clock divisor (also called the DLBR register) that divides the UART clock by an integer multiple of 16. The
second is a baud rate adjustment (also called the DHBR register) that is used to specify a number of UART clock cycles to
stuff in the first or second half of each bit time. Up to eight UART cycles can be inserted into the first half of each bit time,
and up to eight UART clock cycles can be inserted into the end of each bit time.
When setting the baud rate manually, the UART clock divisor is an 8-bit value that is stored as a 256 desired divisor. For
example, a desired divisor of 13 is stored as 256 – 13 = 243 = 0xF3.
The baud rate adjustment is also an 8-bit value, of which the four MSBs are the number of additional clock cycles to insert
in the first half of each bit time, and the four LSBs are the number of clock cycles to insert in the second half of each bit time.
If either of these two values is over eight, it is rounded to eight.
To program the baud rate for high-rate mode (greater than 1.5 Mbaud), divide UART clock by the desired rate to compute
the number of UART clock cycles per bit. This number must be from eight to 15 for the high-rate mode, and is programmed
into the DLBR as 256 minus the number of clocks. For three Mbaud, the calculation would be as follows:
24,000,000/3,000,000 = 8 and 256 – 8 = 248 = 0xF8.
To compute normal 2048 baud rate mode (<1.5 Mbaud), the calculation is expressed as:
24 MHz/((16xUART clock divisor) + total inserted 24 MHz clock cycles)
Table 5 contains example values to generate common baud rates.
Table 5: Common Baud Rate Examples
Baud Rate Adjustment
High Nibble Low Nibble
0x00 0x00
UART Clock
Divisora
Desired Baud
Rate (bps)
Actual Baud Rate
(bps)
Error (%)
4000000
3692000
3000000
2000000
1500000
1444444
921600
460800
230400
115200
57600
0xF4
0xF3
0xF8
0xF4
0xFF
0xFE
0xFF
0xFD
0xFA
0xF3
0xE6
0xD9
0xCC
0xB2
0x98
0x64
4000000
3692308
3000000
2000000
1500000
1454544
923077
461538
230796
115385
57692
0.00
0.01
0.00
0.00
0.00
0.70
0.16
0.16
0.17
0.16
0.16
0.00
0.16
0.00
0.16
0.00
0x00
0x00
0x00
0x00
0x00
0x05
0x02
0x04
0x00
0x00
0x01
0x00
0x01
0x00
0x02
0x00
0x00
0x00
0x00
0x01
0x05
0x02
0x04
0x00
0x00
0x00
0x00
0x01
0x00
0x02
38400
38400
28800
28846
19200
19200
14400
14423
9600
9600
a. The value in this column is 256 minus the desired divisor.
Broadcom Corporation
Document 4325-DS04-R
Bluetooth UART Interface
Page 21
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