BCM4319 Preliminary Data Sheet
SDIO V2.0
The USB 2.0 PHY handles the USB protocol and the serial signaling interface between the host and the device.
It is primarily responsible for data transmission and recovery. On the transmit side, data and a clock are encoded
using the NRZI scheme with bit stuffing to ensure that the receiver detects a transition in the data stream. A
SYNC field that precedes each packet enables the receiver to synchronize the data and clock recovery circuits.
On the receive side, the serial data is deserialized, unstuffed, and checked for errors. The recovered data and
clock are then shifted to the clock domain that is compatible with the internal bus logic.
The endpoint management unit contains the PIE control logic and the endpoint logic. The PIE interfaces the
packet buffers to the USB transceiver. It handles packet identification (PID), USB packets, and transactions. The
endpoint logic contains nine uniquely addressable endpoints. These endpoints are the source or sink of
communication flow between the host and the device. Endpoint zero is used as a default control port for both
the input and output directions. The USB system software uses this default control method to initialize and
configure the device information and allows USB status and control access. Endpoint zero is always accessible
after a device is attached, powered, and reset.
Endpoints are supported by 512-byte FIFO buffers, one for each IN endpoint and one shared by all OUT
endpoints. Both TX and RX data transfers support a DMA burst of 4, which guarantees low latency and
maximum throughput performance. The RX FIFO can never overflow by design. The maximum USB packet size
cannot be more than 512 bytes.
SDIO V2.0
The SDIO Interface is enabled by a strapping option, see Table 8 on page 56 for details.
The BCM4319 supports all of the SDIO version 2.0 modes:
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•
•
•
1-bit SDIO-SPI mode (25 Mbps)
1-bit SDIO-SD mode (25 Mbps)
4-bit SDIO-SD Default Speed mode (100 Mbps)
4-bit SDIO-SD High Speed mode (200 Mbps)
The SDIO interface supports the full clock range, from 0 to 50 MHz.
The chip has the ability to stop the SDIO clock between transactions to reduce power consumption. As an
option, GPIO_0 pin may be mapped to provide an SDIO Interrupt signal. This out-of-band interrupt is hardware
generated and is always valid (unlike the SDIO in-band interrupt, which is signalled only when data is not driven
on SDIO lines).The ability to force control of the gated clocks from within the WLAN chip is also provided.
Three functions are supported:
•
•
Function 0
Function 1
Standard SDIO function. Maximum BlockSize/ByteCount = 32 bytes.
Backplane function to access the internal System-on-a-Chip (SoC) address space.
Maximum BlockSize/ByteCount = 64 bytes.
•
Function 2
WLAN function for efficient WLAN packet transfer through direct memory access (DMA).
Maximum BlockSize/ByteCount = 512 bytes.
Detailed SDIO pin description and signal connection block diagrams are shown in Section 9: “Pinout and Signal
Descriptions,” on page 45. In addition, the generic SPI (gSPI) mode, with clock ranges from 0 to 48 MHz, is
supported.
Broadcom®
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 27
April 2, 2014 • 4319-DS05-R
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