BCM4319 Preliminary Data Sheet
gSPI
Status
The SPI interface supports status notification to the host after a read/write transaction. This status notification
provides information about any packet errors, protocol errors, information about available packet in the RX
queue, etc. The status information helps in reducing the number of interrupts to the Host. The status-reporting
feature can be switched off using a register bit, without any timing overhead. The SPI bus timing for read/write
transactions with and without status notification are as shown in Figure 12 and Figure 13 on page 32. See
Table 2 on page 32 for information on status field details.
Figure 12: SPI Signal Timing Without Status
Write
cs
sclk
mosi
CC3311 CC3300
CC11
Command 32 bits
CC00 DD3311 DD3300
DD11
DD00
DD00
Write Data 16*n bits
Write-Read
cs
sclk
mosi
miso
CC3311 CC3300
CC00
CC00
DD3311 DD3300
DD11
Response
Delay
Command
32 bits
Read Data 16*n bits
cs
Read
sclk
mosi
miso
CC3311 CC3300
DD3311 DD3300
DD00
Command
32 bits
Response
Delay
Read Data
16*n bits
Broadcom®
April 2, 2014 • 4319-DS05-R
Single-Chip IEEE 802.11™ a/b/g/n MAC/Baseband/Radio
Page 31
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