ADVANCE
CYW43143
5. SDIO Interface
The SDIO interface is enabled by a strapping option (see Table 5 on page 21 for details). The CYW43143 supports all of the SDIO
version 2.0 modes:
■ 1-bit SDIO-SPI mode (25 Mbps)
■ 1-bit SDIO-SD mode (25 Mbps)
■ 4-bit SDIO-SD default speed mode (100 Mbps)
■ 4-bit SDIO-SD high speed mode (200 Mbps).
The SDIO interface supports the full clock range from 0 to 50 MHz. The chip has the ability to stop the SDIO clock between transactions
to reduce power consumption. As an option, the GPIO_4 or the GPIO_16 pin can be mapped to provide an SDIO Interrupt signal.
This out-of-band interrupt is hardware generated and is always valid (unlike the SDIO in-band interrupt, which is signalled only when
data is not driven on SDIO lines). The ability to force control of the gated clocks from within the WLAN chip is also provided. Three
functions are supported:
■ Function 0 standard SDIO function. Maximum BlockSize/ByteCount = 32 bytes.
■ Function 1 backplane function to access the internal System-on-a-Chip (SoC) address space. Maximum BlockSize/ ByteCount =
64 bytes.
■ Function 2 WLAN function for efficient WLAN packet transfer through DMA. Maximum BlockSize/ByteCount = 512 bytes.
Document Number: 002-15045 Rev. *F
Page 10 of 44
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