PRELIMINARY
CYW20713
1.2 Block Diagram
Figure 2 on page 6 shows the interconnect of the major CYW20713 physical blocks and associated external interfaces.
Figure 2. Functional Block Diagram
JTAG
ARM7TDMI-S
DMA
Scan JTAG
Address Decoder
Bus Arb
Trap &
Patch
32-bit AHB
Flash
I/F
AHB2EBI
External
Bus I/F
SPIM
AHB2MEM
AHB2MEM
PMU Control
AHB2APB
Remap
& Pause
Interrupt
Controller
WD Timer
ROM
384 KB
RAM
112 KB
USB
SW
Timers
JTAG
Master
GPIO+Aux
PCM
OTP
(128 bytes)
UART
32-bit APB
LCU
Digital
Modulator
Digital
I/O
Buffer
APU
Debug
UART
Calibration &
Control
SPI/EMPSPI
(Spiffy)
Bluetooth Radio
Blue RF I/F
RF
Digital Demod
Bit Sync
BT Clk/
Hopper
I2C_Master
FIFO 1
Low Power
Scan
Rx/Tx
Buffer
Blue RF Registers
COEX
SECI
FIFO 2
PMU
LPO
POR
PTU
Document Number: 002-14806 Rev. *C
Page 6 of 52
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