CYW20704
Figure 22 and Table 29 define the timing requirements when operating in SPI Mode 1 and 3.
Figure 22. SPI Timing, Mode 1 and 3
SPI_CSN
5
SPI_INT
(DirectWrite)
3
4
SPI_INT
(DirectRead)
SPI_CLK
1
(Mode 1)
SPI_CLK
(Mode 3)
2
Invalid bit
Invalid bit
First bit
First bit
Last bit
Last bit
SPI_MOSI
SPI_MISO
Not Driven
Not Driven
Table 29. SPI Mode 1 and 3
Reference
Characteristics
Minimum
Maximum
Unit
ns
1
2
3
Time from master assert SPI_CSN to first clock edge
Hold time for MOSI data lines
45
12
0
–
½ SCK
100
ns
ns
Time from last sample on MOSI/MISO to slave
deassert SPI_INT
4
5
Time from slave deassert SPI_INT to master
deassert SPI_CSN
0
–
–
ns
ns
Idle time between subsequent SPI transactions
1 SCK
Document Number: 002-14786 Rev. *E
Page 44 of 49
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