CYW20704
9.3.3 SPI Timing
The SPI interface can be clocked up to 12 MHz.
Figure 21 and Table 28 define the timing requirements when operating in SPI Mode 0 and 2.
Figure 21. SPI Timing, Mode 0 and 2
5
SPI_CSN
SPI_INT
(DirectWrite)
SPI_INT
(DirectRead)
1
SPI_CLK
(Mode 0)
SPI_CLK
(Mode 2)
2
First Bit
Second Bit
Second Bit
Last bit
Last bit
SPI_MOSI
SPI_MISO
First Bit
Not Driven
Not Driven
Table 28. SPI Mode 0 and 2
Reference
Characteristics
Minimum
Maximum
Unit
ns
1
2
3
4
5
Time from master assert SPI_CSN to first clock edge
Hold time for MOSI data lines
45
–
12
½ SCK
100
ns
ns
ns
ns
Time from last sample on MOSI/MISO to slave deassert SPI_INT
Time from slave deassert SPI_INT to master deassert SPI_CSN
Idle time between subsequent SPI transactions
0
0
–
1 SCK
–
Document Number: 002-14786 Rev. *E
Page 43 of 49
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