CYW20704
9.3.2 BSC Interface Timing
Figure 20 and Table 27 define the timing requirements for the BSC interface.
Figure 20. BSC Interface Timing Diagram
1
5
SCL
2
4
7
8
6
3
SDA
IN
10
9
SDA
OUT
Table 27. BSC Interface Timing Specifications
Reference Characteristics
Minimum
Maximum
100
Unit
kHz
1
Clock frequency
–
400
800
1000
2
3
4
5
6
7
8
9
START condition setup time
START condition hold time
Clock low time
650
280
650
280
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
Clock high time
–
Data input hold timea
Data input setup time
STOP condition setup time
Output valid from clock
Bus free timeb
–
100
280
–
–
–
400
–
10
650
a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions
b. Time that the cbus must be free before a new transaction can start.
Document Number: 002-14786 Rev. *E
Page 42 of 49
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