CYW20704
9.2.4 PCM Interface Timing
Short Frame Sync, Master Mode
Figure 12. PCM Timing Diagram (Short Frame Sync, Master Mode)
1
2
3
PCM_BCLK
4
PCM_SYNC
8
PCM_OUT
5
HIGH IMPEDANCE
7
6
PCM_IN
Table 21. PCM Interface Timing Specifications (Short Frame Sync, Master Mode)
Ref No. Characteristics Minimum
Typical
Maximum
12
Unit
MHz
1
2
3
4
5
6
7
8
PCM bit clock frequency
PCM bit clock LOW
PCM bit clock HIGH
PCM_SYNC delay
PCM_OUT delay
PCM_IN setup
–
–
–
–
–
–
–
–
–
41
41
0
–
ns
ns
ns
ns
ns
ns
ns
–
25
25
–
0
8
PCM_IN hold
8
–
Delay from rising edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
0
25
Document Number: 002-14786 Rev. *E
Page 33 of 49
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