CYW20704
9.2 Timing and AC Characteristics
In this section, use the numbers listed in the reference column to interpret the timing diagrams.
9.2.1 Startup Timing
The global reset signal in the CYW20704 is a logical OR (actually a wired AND, since the signals are active low) of the RST_N input
and the internal POR signals. The last signal to be released determines the time at which the chip is released from reset. The POR
is typically asserted for 2.4 ms after the POR threshold is crossed.
The following two figures illustrate two startup timing scenarios.
Figure 9. Startup Timing
ꢀ3.96 ms
VDDO
~ 2.4 ms
VDDO POR
0.5 ms
VDDC
7.5 ms
VDDC Reset
VDDC Reset/Share XTAL
9.2.2 USB Full-Speed Timing
Table 19 through Table 10 shows timing specifications for VDD_USB = 3.3V, V = 0V, and T = 0°C to 85°C operating
SS
A
temperature range.
Table 19. USB Full-Speed Timing Specifications
Reference
Characteristics
Minimum
Maximum
20
Unit
1
2
3
4
Transition rise time
Transition fall time
4
4
ns
ns
%
20
Rise/fall timing matching
Full-speed data rate
90
12 – 0.25%
111
12 + 0.25%
Mb/s
Figure 10. USB Full-Speed Timing
2
1
D+
90%
90%
VCRS
10%
10%
D-
Document Number: 002-14786 Rev. *E
Page 31 of 49
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