To respond to the SOF interrupt, the 8051 clears the USB interrupt (8051 INT2), and
clears the SOFIR bit by writing one to it. Then, the 8051 reads data from the appropriate
OUTnDATA FIFO register(s). The 8051 can check an error bit in the ISOERR register to
determine if a CRC error occurred for the endpoint data. Isochronous data is never
present, so the firmware must decide what to do with bad-CRC data.
8.4
Setting Isochronous FIFO Sizes
Up to sixteen EZ-USB isochronous endpoints share an EZ-USB 1,024-byte RAM which
can be configured as one to sixteen FIFOs. The 8051 initializes the endpoint FIFO sizes
by specifying the starting address for each FIFO within the 1,024 bytes, starting at address
zero. The isochronous FIFOs can exist anywhere in the 1,024 bytes, but the user must
take care to ensure that there is sufficient space between start addresses to accommodate
the endpoint FIFO size.
Sixteen start address registers set the isochronous FIFO sizes (Table 8-1). The EZ-USB
core constructs the address writing the 1,024 byte range from the register value as shown
in Figure 8-4.
Address
A9
A8
A7
A6
A5
A4
0
0
0
0
Register
Figure 8-4. FIFO Start Address Format
EZ-USB TRM v1.9
Chapter 8. EZ-USB CPU
Page 8-5
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