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AM49DL323BGB85IS 参数 Datasheet PDF下载

AM49DL323BGB85IS图片预览
型号: AM49DL323BGB85IS
PDF下载: 下载PDF文件 查看货源
内容描述: [Memory Circuit, Flash+PSRAM, CMOS, PBGA73,]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 64 页 / 1054 K
品牌: CYPRESS [ CYPRESS ]
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P R E L I M I N A R Y  
cles, determining the status as described in the  
DQ2: Toggle Bit II  
previous paragraph. Alternatively, it may choose to  
perform other system tasks. In this case, the system  
must start at the beginning of the algorithm when it re-  
turns to determine the status of the operation (top of  
Figure 6).  
The Toggle Bit IIon DQ2, when used with DQ6, indi-  
cates whether a particular sector is actively erasing  
(that is, the Embedded Erase algorithm is in progress),  
or whether that sector is erase-suspended. Toggle Bit  
II is valid after the rising edge of the final WE# pulse in  
the command sequence.  
DQ5: Exceeded Timing Limits  
DQ2 toggles when the system reads at addresses  
within those sectors that have been selected for era-  
sure. (The system may use either OE# or CE#f to  
control the read cycles.) But DQ2 cannot distinguish  
whether the sector is actively erasing or is erase-sus-  
pended. DQ6, by comparison, indicates whether the  
device is actively erasing, or is in Erase Suspend, but  
cannot distinguish which sectors are selected for era-  
sure. Thus, both status bits are required for sector and  
mode information. Refer to Table 18 to compare out-  
puts for DQ2 and DQ6.  
DQ5 indicates whether the program or erase time  
has exceeded a specified internal pulse count limit.  
Under these conditions DQ5 produces a 1,indicating  
that the program or erase cycle was not successfully  
completed.  
The device may output a 1on DQ5 if the system tries  
to program a 1to a location that was previously pro-  
grammed to 0.Only an erase operation can  
change a 0back to a 1.Under this condition, the  
device halts the operation, and when the timing limit  
has been exceeded, DQ5 produces a 1.”  
Figure 6 shows the toggle bit algorithm in flowchart  
form, and the section DQ2: Toggle Bit IIexplains the  
algorithm. See also the DQ6: Toggle Bit I subsection.  
Figure 23 shows the toggle bit timing diagram. Figure  
24 shows the differences between DQ2 and DQ6 in  
graphical form.  
Under both these conditions, the system must write  
the reset command to return to reading array data (or  
to the erase-suspend-read mode if a bank was previ-  
ously in the erase-suspend-program mode).  
DQ3: Sector Erase Timer  
Reading Toggle Bits DQ6/DQ2  
After writing a sector erase command sequence, the  
system may read DQ3 to determine whether or not  
erasure has begun. (The sector erase timer does not  
apply to the chip erase command.) If additional  
sectors are selected for erasure, the entire time-out  
also applies after each additional sector erase com-  
mand. When the time-out period is complete, DQ3  
switches from a 0to a 1.If the time between addi-  
tional sector erase commands from the system can be  
assumed to be less than 50 µs, the system need not  
monitor DQ3. See also the Sector Erase Command  
Sequence section.  
Refer to Figure 6 for the following discussion. When-  
ever the system initially begins reading toggle bit  
status, it must read DQ7DQ0 at least twice in a row  
to determine whether a toggle bit is toggling. Typically,  
the system would note and store the value of the tog-  
gle bit after the first read. After the second read, the  
system would compare the new value of the toggle bit  
with the first. If the toggle bit is not toggling, the device  
has completed the program or erase operation. The  
system can read array data on DQ7DQ0 on the fol-  
lowing read cycle.  
After the sector erase command is written, the system  
should read the status of DQ7 (Data# Polling) or DQ6  
(Toggle Bit I) to ensure that the device has accepted  
the command sequence, and then read DQ3. If DQ3 is  
1,the Embedded Erase algorithm has begun; all fur-  
ther commands (except Erase Suspend) are ignored  
until the erase operation is complete. If DQ3 is 0,the  
device will accept additional sector erase commands.  
To ensure the command has been accepted, the sys-  
tem software should check the status of DQ3 prior to  
and following each subsequent sector erase com-  
mand. If DQ3 is high on the second status check, the  
last command might not have been accepted.  
However, if after the initial two read cycles, the system  
determines that the toggle bit is still toggling, the sys-  
tem also should note whether the value of DQ5 is high  
(see the section on DQ5). If it is, the system should  
then determine again whether the toggle bit is tog-  
gling, since the toggle bit may have stopped toggling  
just as DQ5 went high. If the toggle bit is no longer  
toggling, the device has successfully completed the  
program or erase operation. If it is still toggling, the de-  
vice did not completed the operation successfully, and  
the system must write the reset command to return to  
reading array data.  
The remaining scenario is that the system initially de-  
termines that the toggle bit is toggling and DQ5 has  
not gone high. The system may continue to monitor  
the toggle bit and DQ5 through successive read cy-  
Table 18 shows the status of DQ3 relative to the other  
status bits.  
34  
Am49DL32xBG  
July 19, 2002