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AM49DL323BGB85IS 参数 Datasheet PDF下载

AM49DL323BGB85IS图片预览
型号: AM49DL323BGB85IS
PDF下载: 下载PDF文件 查看货源
内容描述: [Memory Circuit, Flash+PSRAM, CMOS, PBGA73,]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 64 页 / 1054 K
品牌: CYPRESS [ CYPRESS ]
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P R E L I M I N A R Y  
WRITE OPERATION STATUS  
The device provides several bits to determine the sta-  
tus of a program or erase operation: DQ2, DQ3, DQ5,  
DQ6, and DQ7. Table 18 and the following subsec-  
tions describe the function of these bits. DQ7 and DQ6  
each offer a method for determining whether a pro-  
gram or erase operation is complete or in progress.  
The device also provides a hardware-based output  
signal, RY/BY#, to determine whether an Embedded  
Program or Erase operation is in progress or has been  
completed.  
pleted the program or erase operation and DQ7 has  
valid data, the data outputs on DQ6DQ0 may be still  
invalid. Valid data on DQ7DQ0 will appear on suc-  
cessive read cycles.  
Table 18 shows the outputs for Data# Polling on DQ7.  
Figure 5 shows the Data# Polling algorithm. Figure 22  
in the pSRAM AC Characteristics section shows the  
Data# Polling timing diagram.  
DQ7: Data# Polling  
START  
The Data# Polling bit, DQ7, indicates to the host sys-  
tem whether an Embedded Program or Erase  
algorithm is in progress or completed, or whether a  
bank is in Erase Suspend. Data# Polling is valid after  
the rising edge of the final WE# pulse in the command  
sequence.  
Read DQ7DQ0  
Addr = VA  
During the Embedded Program algorithm, the device  
outputs on DQ7 the complement of the datum pro-  
grammed to DQ7. This DQ7 status also applies to  
programming during Erase Suspend. When the Em-  
bedded Program algorithm is complete, the device  
outputs the datum programmed to DQ7. The system  
must provide the program address to read valid status  
information on DQ7. If a program address falls within a  
protected sector, Data# Polling on DQ7 is active for  
approximately 1 µs, then that bank returns to reading  
array data.  
Yes  
DQ7 = Data?  
No  
No  
DQ5 = 1?  
Yes  
During the Embedded Erase algorithm, Data# Polling  
produces a 0on DQ7. When the Embedded Erase  
algorithm is complete, or if the bank enters the Erase  
Suspend mode, Data# Polling produces a 1on DQ7.  
The system must provide an address within any of the  
sectors selected for erasure to read valid status infor-  
mation on DQ7.  
Read DQ7DQ0  
Addr = VA  
Yes  
DQ7 = Data?  
After an erase command sequence is written, if all  
sectors selected for erasing are protected, Data# Poll-  
ing on DQ7 is active for approximately 100 µs, then  
the bank returns to reading array data. If not all se-  
lected sectors are protected, the Embedded Erase  
algorithm erases the unprotected sectors, and ignores  
the selected sectors that are protected. However, if the  
system reads DQ7 at an address within a protected  
sector, the status may not be valid.  
No  
PASS  
FAIL  
Notes:  
1. VA = Valid address for programming. During a sector  
erase operation, a valid address is any sector address  
within the sector being erased. During chip erase, a  
valid address is any non-protected sector address.  
Just prior to the completion of an Embedded Program  
or Erase operation, DQ7 may change asynchronously  
with DQ0DQ6 while Output Enable (OE#) is asserted  
low. That is, the device may change from providing  
status information to valid data on DQ7. Depending on  
when the system samples the DQ7 output, it may read  
the status or valid data. Even if the device has com-  
2. DQ7 should be rechecked even if DQ5 = 1because  
DQ7 may change simultaneously with DQ5.  
Figure 5. Data# Polling Algorithm  
32  
Am49DL32xBG  
July 19, 2002