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AM49DL323BGB85IS 参数 Datasheet PDF下载

AM49DL323BGB85IS图片预览
型号: AM49DL323BGB85IS
PDF下载: 下载PDF文件 查看货源
内容描述: [Memory Circuit, Flash+PSRAM, CMOS, PBGA73,]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 64 页 / 1054 K
品牌: CYPRESS [ CYPRESS ]
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P R E L I M I N A R Y  
DQ6 also toggles during the erase-suspend-program  
RY/BY#: Ready/Busy#  
mode, and stops toggling once the Embedded Pro-  
gram algorithm is complete.  
The RY/BY# is a dedicated, open-drain output pin  
which indicates whether an Embedded Algorithm is in  
progress or complete. The RY/BY# status is valid after  
the rising edge of the final WE# pulse in the command  
sequence. Since RY/BY# is an open-drain output, sev-  
eral RY/BY# pins can be tied together in parallel with a  
Table 18 shows the outputs for Toggle Bit I on DQ6.  
Figure 6 shows the toggle bit algorithm. Figure 23 in  
the Flash AC Characteristicssection shows the tog-  
gle bit timing diagrams. Figure 24 shows the  
differences between DQ2 and DQ6 in graphical form.  
See also the subsection on DQ2: Toggle Bit II.  
pull-up resistor to VCC  
.
If the output is low (Busy), the device is actively eras-  
ing or programming. (This includes programming in  
the Erase Suspend mode.) If the output is high  
(Ready), the device is reading array data, the standby  
mode, or one of the banks is in the erase-sus-  
pend-read mode.  
START  
Table 18 shows the outputs for RY/BY#.  
Read DQ7DQ0  
DQ6: Toggle Bit I  
Toggle Bit I on DQ6 indicates whether an Embedded  
Program or Erase algorithm is in progress or com-  
plete, or whether the device has entered the Erase  
Suspend mode. Toggle Bit I may be read at any ad-  
dress, and is valid after the rising edge of the final  
WE# pulse in the command sequence (prior to the  
program or erase operation), and during the sector  
erase time-out.  
Read DQ7DQ0  
No  
Toggle Bit  
= Toggle?  
During an Embedded Program or Erase algorithm op-  
eration, successive read cycles to any address cause  
DQ6 to toggle. The system may use either OE# or  
CE#f to control the read cycles. When the operation is  
complete, DQ6 stops toggling.  
Yes  
No  
DQ5 = 1?  
Yes  
After an erase command sequence is written, if all  
sectors selected for erasing are protected, DQ6 tog-  
gles for approximately 100 µs, then returns to reading  
array data. If not all selected sectors are protected, the  
Embedded Erase algorithm erases the unprotected  
sectors, and ignores the selected sectors that are  
protected.  
Read DQ7DQ0  
Twice  
The system can use DQ6 and DQ2 together to deter-  
mine whether a sector is actively erasing or is  
erase-suspended. When the device is actively erasing  
(that is, the Embedded Erase algorithm is in progress),  
DQ6 toggles. When the device enters the Erase Sus-  
pend mode, DQ6 stops toggling. However, the system  
must also use DQ2 to determine which sectors are  
erasing or erase-suspended. Alternatively, the system  
can use DQ7 (see the subsection on DQ7: Data#  
Polling).  
Toggle Bit  
= Toggle?  
No  
Yes  
Program/Erase  
Operation Not  
Complete, Write  
Reset Command  
Program/Erase  
Operation Complete  
If a program address falls within a protected sector,  
DQ6 toggles for approximately 1 µs after the program  
command sequence is written, then returns to reading  
array data.  
Note: The system should recheck the toggle bit even if DQ5  
= 1because the toggle bit may stop toggling as DQ5  
changes to 1.See the subsections on DQ6 and DQ2 for  
more information.  
Figure 6. Toggle Bit Algorithm  
July 19, 2002  
Am49DL32xBG  
33