D A T A S H E E T
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
Test Setup
-45
-50
-55
-70
-90
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Min
45
50
50
55
70
70
90
ns
CE# = VIL
Max
tAVQV
tACC Address to Output Delay
45
55
90
ns
OE# = VIL
tELQV
tGLQV
tCE
tOE
Chip Enable to Output Delay
Output Enable to Output Delay
OE# = VIL
Max
Max
45
30
50
30
55
30
70
30
90
35
ns
ns
Chip Enable to Output High Z
(Note 1)
tEHQZ
tDF
Max
15
15
15
15
15
20
20
20
20
ns
Output Enable to Output High Z
(Note 1)
tGHQZ
tDF
Max
Min
Min
15
0
ns
ns
ns
Read
Output Enable
tOEH Hold Time
(Note 1)
Toggle and
Data# Polling
10
Output Hold Time From
Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
tAXQX
tOH
Min
0
ns
Notes:
1. Not 100% tested.
2. See Figure 8 and Table 7 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 9. Read Operations Timings
26
Am29F400B
21505E8 November 11, 2009
CYPRESS [ CYPRESS ]
