CY7C4282V
CY7C4292V
Pin Configuration
WCLK
XI/LD
GND
N/C
N/C
N/C
N/C
N/C
V
CC
N/C
N/C
Q
8
Q
7
GND
Q
6
N/C
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
STQFP
Top View
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
WEN
RS
D
8
D
7
D
6
N/C
N/C
N/C
N/C
N/C
N/C
N/C
D
5
D
4
D
3
D
2
CY7C4282V
CY7C4292V
Q
5
Q
4
GND
Q
3
Q
2
V
CC
Q
1
Q
0
GND
N/C
FF
EF
OE
GND
FL/RT
N/C
4282V–2
Functional Description
(continued)
The CY7C4282V/92V provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to sin-
gle word granularity. The programmable flags default to Emp-
ty+7 and Full−7.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
Selection Guide
7C4282V/92V-10
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (I
CC
) (mA)
Commercial
Industrial
100
8
10
3.5
0
8
25
7C4282V/92V-15
66.7
10
15
4
0
10
25
30
7C4282V/92V-25
40
15
25
6
1
15
25
D
1
D
0
N/C
N/C
N/C
V
CC
PAF/XO
PAE
N/C
N/C
N/C
N/C
N/C
GND
REN
RCLK
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle
All configurations are fabricated using an advanced 0.35µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
CY7C4282V
Density
Package
64k x 9
64-pin 10x10 TQFP
CY7C4292V
128k x 9
64-pin 10x10 TQFP
2
CYPRESS [ CYPRESS SEMICONDUCTOR ]
