CY7C4282V
CY7C4292V
Switching Waveforms
(continued)
Reset Timing
[13]
[12]
t
RSS
LD
t
RS
RS
t
RSR
REN, WEN
t
RSF
EF,PAE
t
RSF
FF,PAF
t
RSF
Q
0 –
Q
8
OE=0
4282V–8
[14]
OE=1
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t
DS
D
0
–D
8
t
ENS
WEN
t
SKEW1
RCLK
t
REF
EF
D
0
(FIRSTVALID WRITE)
[15]
D
1
D
2
D
3
D
4
t
FRL
REN
[16]
t
A
Q
0
–Q
8
t
OLZ
t
OE
OE
t
A
D
0
D
1
4282V–9
Notes:
12. The clocks (RCLK, WCLK) can be free-running during reset.
13. For standalone or width expansion configuration only.
14. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
15. When t
SKEW1
> minimum specification, t
FRL
(maximum) = t
CLK
+ t
SKEW2
. When t
SKEW1
< minimum specification, t
FRL
(maximum) = either 2*t
CLK
+ t
SKEW1
or t
CLK
+ t
SKEW1
.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
16. The first word is available the cycle after EF goes HIGH, always.
7
CYPRESS [ CYPRESS SEMICONDUCTOR ]
