CY7C4282V
CY7C4292V
64K/128Kx9 Low Voltage Deep Sync FIFOs
w/ Retransmit & Depth Expansion
Features
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO)
memories
• 64K x 9 (CY7C4282V)
• 128K x 9 (CY7C4292V)
• 0.35 micron CMOS for optimum speed/power
• High-speed, Near Zero Latency (True Dual-Ported
Memory Cell), 100-MHz operation (10 ns read/write
cycle times)
• Low power
—
I
CC
= 25 mA
•
•
•
•
•
•
•
•
•
•
—
I
SB
= 6 mA
Fully asynchronous and simultaneous read and write
operation
Empty, Full, and Programmable Almost Empty and Al-
most Full status flags
Retransmit function
Output Enable (OE) pin
Independent read and write enable pins
Supports free-running 50% duty cycle clock inputs
Width Expansion Capability
Depth Expansion Capability through token-passing
scheme (no external logic required)
64-pin 10x10 STQFP
Pin-compatible 3.3V solution for CY7C4282/92
Functional Description
The CY7C4282V/92V are high-speed, low-power, first-in first-
out (FIFO) memories with clocked read and write interfaces.
All devices are 9 bits wide. The CY7C4282V/92V can be cas-
caded to increase FIFO depth. Programmable features include
Almost Full/Almost Empty flags. These FIFOs provide solutions
for a wide variety of data buffering needs, including high-speed data
acquisition, multiprocessor interfaces, video and communications
buffering.
These FIFOs have 9-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a Write Enable
pin (WEN).
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the Cascade Input (XI), Cas-
cade Output (XO), and First Load (FL) pins. The XO pin is connected
to the XI pin of the next device, and the XO pin of the last device
should be connected to the XI pin of the first device. The FL pin of the
first device is tied to V
SS
and the FL pin of all the remaining devices
should be tied to V
CC
When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data
is continually written into the FIFO on each cycle. The output
port is controlled in a similar manner by a free-running Read
Clock (RCLK) and a Read Enable pin (REN). In addition, the
CY7C4282V/92V have an Output Enable pin (OE). The read
and write clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 67 MHz are
achievable.
D
0
−
8
Logic Block Diagram
INPUT
REGISTER
WCLK WEN
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
FF
FLAG
LOGIC
Dual Port
RAM Array
64K x 9
128K x 9
READ
POINTER
EF
PAE
PAF/XO
WRITE
POINTER
RS
RESET
LOGIC
FL/RT
XI/LD
PAF/XO
EXPANSION
LOGIC
THREE-STATE
OUTPUT REGISTER
OE
Q
0
−
8
READ
CONTROL
RCLK REN
4282V–1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 18, 1999
CYPRESS [ CYPRESS SEMICONDUCTOR ]
