Ultra37000 CPLD Family
Typical 3.3V Power Consumption (continued)
CY37384V
200
180
160
140
120
100
80
H igh S peed
Low P ow er
60
40
20
0
0
10
20
30
40
50
60
70
80
90
F req u e n cy (M H z)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
= 3.3V, T = Room Temperature
V
CC
A
CY37512V
2 5 0
2 0 0
1 5 0
1 0 0
5 0
H ig h S p e e d
L o w P o w e r
0
0
1 0
2 0
3 0
4 0
5 0
6 0
7 0
8 0
9 0
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
= 3.3V, T = Room Temperature
V
CC
A
Document #: 38-03007 Rev. *E
Page 30 of 64
CYPRESS [ CYPRESS ]
