Ultra37000 CPLD Family
Typical 3.3V Power Consumption (continued)
CY37192V
1 2 0
1 0 0
8 0
6 0
4 0
2 0
0
H ig h S p e e d
L o w P o w e r
0
2 0
4 0
6 0
F re q u e n c y (M H z)
8 0
1 0 0
1 2 0
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
= 3.3V, T = Room Temperature
A
CC
CY37256V
1 4 0
1 2 0
1 0 0
8 0
H ig h S p e e d
L o w P o w e r
6 0
4 0
2 0
0
0
2 0
4 0
6 0
8 0
1 0 0
1 2 0
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
= 3.3V, T = Room Temperature
V
CC
A
Document #: 38-03007 Rev. *E
Page 29 of 64
CYPRESS [ CYPRESS ]
