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5962-9952201QYX 参数 Datasheet PDF下载

5962-9952201QYX图片预览
型号: 5962-9952201QYX
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 15ns, CMOS, CQCC84, CERAMIC, LCC-84]
分类和应用: 时钟输入元件可编程逻辑
文件页数/大小: 64 页 / 2085 K
品牌: CYPRESS [ CYPRESS ]
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Ultra37000 CPLD Family  
Typical 3.3V Power Consumption (continued)  
CY37064V  
45  
40  
35  
30  
25  
20  
15  
10  
5
High Speed  
Low Power  
0
0
20  
40  
60  
80  
100  
120  
140  
Frequency (MHz)  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
V
= 3.3V, T = Room Temperature  
A
CC  
CY37128V  
80  
70  
60  
50  
40  
30  
20  
10  
0
H igh S peed  
Low P ow er  
0
20  
40  
60  
80  
100  
120  
140  
F re q u en c y (M H z)  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
= 3.3V, T = Room Temperature  
V
CC  
A
Document #: 38-03007 Rev. *E  
Page 28 of 64  
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