Ultra37000 CPLD Family
Logic Block Diagrams (continued)
Clock/
Input
Input
1
CY37256/CY37256V (256-lead BGA)
4
4
4
36
16
36
16
36
36
LOGIC
BLOCK
A
LOGIC
BLOCK
P
12 I/Os
11
12 I/Os
I/O −I/O
16
36
I/O −I/O
180
191
179
0
12 I/Os
I/O −I/O
12 I/Os
LOGIC
BLOCK
B
LOGIC
BLOCK
O
16
36
16
36
16
I/O −I/O
168
12
23
12 I/Os
I/O −I/O
12 I/Os
LOGIC
BLOCK
C
LOGIC
BLOCK
N
I/O −I/O
16
36
16
36
16
156
167
155
24
35
12 I/Os
I/O −I/O
12 I/Os
47
LOGIC
BLOCK
D
LOGIC
BLOCK
M
I/O −I/O
144
36
PIM
36
16
36
12 I/Os
I/O −I/O
12 I/Os
59
LOGIC
BLOCK
E
LOGIC
BLOCK
L
I/O −I/O
48
132
143
131
36
16
12 I/Os
I/O −I/O
12 I/Os
LOGIC
BLOCK
F
LOGIC
BLOCK
K
I/O −I/O
16
36
16
120
60
71
36
16
36
12 I/Os
I/O −I/O
12 I/Os
83
LOGIC
BLOCK
G
LOGIC
BLOCK
J
I/O −I/O
72
108
119
36
16
12 I/Os
I/O −I/O
12 I/Os
LOGIC
BLOCK
H
LOGIC
BLOCK
I
16
I/O −I/O
96
107
84
95
TDI
TCK
TMS
96
96
JTAG Tap
Controller
TDO
Document #: 38-03007 Rev. *D
Page 11 of 64
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