Delta39K™ ISR™
CPLD Family
Cluster Memory Timing Parameter Descriptions Over the Operating Range (continued)
Parameter
tMACCLMS2
Internal Parameters
tCLMCLAA Asynchronous cluster memory access time from input of cluster memory to output of cluster memory
Description
Macrocell clock to cluster memory output clock in the same cluster
Channel Memory Timing Parameter Descriptions Over the Operating Range
Parameter
Description
Dual Port Asynchronous Mode Parameters
tCHMAA
tCHMPWE
tCHMSA
tCHMHA
tCHMSD
tCHMHD
tCHMBA
Channel memory access time. Delay from address change to Read data out
Write enable pulse width
Address set-up to the beginning of Write enable with both signals from the same I/O block
Address hold after the end of Write enable with both signals from the same I/O block
Data set-up to the end of Write enable
Data hold after the end of Write enable
Channel memory asynchronous dual port address match (busy access time)
Dual Port Synchronous Mode Parameters
Clock cycle time for flow through Read and Write operations (from macrocell register through channel
memory back to a macrocell register in the same cluster)
tCHMCYC1
tCHMCYC2
Clock cycle time for pipelined Read and Write operations (from channel memory input register through the
memory to channel memory output register)
tCHMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
Address, data, and WE hold time of pin inputs, relative to a global clock
Global clock to data valid on output pins for flow through data
tCHMH
tCHMDV1
tCHMDV2
tCHMBDV
tCHMMACS1
tCHMMACS2
tMACCHMS1
tMACCHMS2
Global clock to data valid on output pins for pipelined data.
Channel memory synchronous dual-port address match (busy, clock to data valid)
Channel memory input clock to macrocell clock in the same cluster
Channel memory output clock to macrocell clock in the same cluster
Macrocell clock to channel memory input clock in the same cluster
Macrocell clock to channel memory output clock in the same cluster
Synchronous FIFO Data Parameters
tCHMCLK Read and Write minimum clock cycle time
tCHMFS
Data, Read enable, and Write enable set-up time relative to pin inputs
Data, Read enable, and Write enable hold time relative to pin inputs
Data access time to output pins from rising edge of Read clock (Read clock to data valid)
Channel memory FIFO Read clock to macrocell clock for Read data
Macrocell clock to channel memory FIFO Write clock for Write data
tCHMFH
tCHMFRDV
tCHMMACS
tMACCHMS
Synchronous FIFO Flag Parameters
tCHMFO
Read or Write clock to respective flag output at output pins
tCHMMACF
tCHMFRS
Read or Write clock to macrocell clock with FIFO flag
Master Reset Pulse Width
tCHMFRSR
tCHMFRSF
tCHMSKEW1
tCHMSKEW2
tCHMSKEW3
Master Reset Recovery Time
Master Reset to Flag and Data Output Time
Read/Write Clock Skew Time for Full Flag
Read/Write Clock Skew Time for Empty Flag
Read/Write Clock Skew Time for Boundary Flags
Document #: 38-03039 Rev. *H
Page 20 of 86
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