Delta39K™ ISR™
CPLD Family
Switching Characteristics — Parameter Descriptions Over the Operating Range[13]
Parameter
Description
Combinatorial Mode Parameters
Delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output on the
horizontal or vertical channel associated with that cluster
tPD
tEA
tER
Global control to output enable
Global control to output disable
Asynchronous macrocell RESET or PRESET recovery time from any pin input on the horizontal or vertical channel
associated with the cluster the macrocell is in
tPRR
tPRO
tPRW
Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical channel associated
with the cluster that the macrocell is in to any pin output on those same channels
Asynchronous macrocell RESET or PRESET minimum pulse width, from any pin input to a macrocell in the farthest
cluster on the horizontal or vertical channel the pin is associated with
Synchronous Clocking Parameters
Set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a
global clock
tMCS
Hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a
global clock
tMCH
tMCCO
Global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with the
cluster that macrocell is in
tIOS
Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global clock
Hold time of any input pin to the I/O cell register associated with that pin, relative to a global clock
Clock to output of an I/O cell register to the output pin associated with that register
tIOH
tIOCO
tSCS
tSCS2
tICS
Macrocell clock to macrocell clock through array logic within the same cluster
Macrocell clock to macrocell clock through array logic in different clusters on the same channel
I/O register clock to any macrocell clock in a cluster on the channel the I/O register is associated with
Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with the cluster that the
macrocell is in
tOCS
tCHZ
tCLZ
fMAX
Clock to output disable (high-impedance)
Clock to output enable (low-impedance)
Maximum frequency with internal feedback—within the same cluster
Maximum frequency with internal feedback—within different clusters at the opposite ends of a horizontal or vertical
channel
fMAX2
Product Term Clock
tMCSPT
tMCHPT
tMCCOPT
tSCS2PT
Set-up time for macrocell used as input register, from input to product term clock
Hold time of macrocell used as an input register
Product term clock to output delay from input pin
Register to register delay through array logic in different clusters on the same channel using a product term clock
Channel Interconnect Parameters
tCHSW Adder for a signal to switch from a horizontal to vertical channel and vice-versa
tCL2CL Cluster-to-cluster delay adder (through channels and channel PIM)
Miscellaneous Delays
Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster PIM input. This parameter
can be added to the tPD and tSCS parameters for each extra pass through the AND/OR array required by a given
signal path
tCPLD
tMCCD
tIOD
Adder for carry chain logic per macrocell
Delay from the input of the output buffer to the I/O pin
Delay from the I/O pin to the input of the channel buffer
tIOIN
Note:
13. Add tCHSW to signals making a horizontal to vertical channel switch or vice-versa.
Document #: 38-03039 Rev. *H
Page 18 of 86
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