Delta39K™ ISR™
CPLD Family
Capacitance
Parameter
Description
Test Conditions
Vin = VCCIO @ f = 1 MHz 25°C
Vin = VCCIO @ f = 1 MHz 25°C
Vin = VCCIO @ f = 1 MHz 25°C
Min.
Max.
10
Unit
pF
CI/O
Input/Output Capacitance
Clock Signal Capacitance
PCI-compliant[9] Capacitance
CCLK
CPCI
5
12
pF
8
pF
DC Characteristics (I/O)[10]
VOH (V)
VOH (min.)
VOL (V)
VOL
VIH (V)
VIL (V)
VREF VCCIO
I/O Standards (V)
LVTTL –2 mA N/A
LVTTL –4 mA
LVTTL –6 mA
LVTTL –8 mA
LVTTL –12 mA
LVTTL –16 mA
LVTTL –24 mA
LVCMOS
(V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.0
2.5
@ IOH
=
@ IOL
2 mA
4 mA
6 mA
8 mA
=
(max.)
Min.
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
1.7V
Max.
Min.
Max.
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.7V
–2 mA
–4 mA
2.4
2.4
2.4
2.4
2.4
2.4
2.4
0.4
VCCIO + 0.3 –0.3V
CCIO + 0.3 –0.3V
VCCIO + 0.3 –0.3V
CCIO + 0.3 –0.3V
VCCIO + 0.3 –0.3V
CCIO + 0.3 –0.3V
0.4
V
–6 mA
0.4
–8 mA
0.4
V
–12 mA
–16 mA
–24 mA
–0.1 mA
12 mA
16 mA
24 mA
0.4
0.4
V
0.4
VCCIO + 0.3 –0.3V
VCCIO + 0.3 –0.3V
VCCIO + 0.3 –0.3V
V
CCIO – 0.2V 0.1 mA
0.2
LVCMOS3
–0.1 mA VCCIO – 0.2V 0.1 mA
0.2
–0.1 mA
–1.0 mA
–2.0 mA
2.1
2.0
1.7
0.1 mA
1.0 mA
2.0 mA
0.2
VCCIO + 0.3 –0.3V
LVCMOS2
0.4
0.7
LVCMOS18
3.3V PCI
1.8
–2 mA VCCIO – 0.45V 2.0 mA
0.45
0.65VCCIO VCCIO + 0.3 –0.3V 0.35VCCIO
3.3
[11]
–0.5 mA
0.9VCCIO
1.5 mA 0.1VCCIO 0.5VCCIO VCCIO + 0.5 –0.5V 0.3VCCIO
36 mA[12]
GTL+
1.0
1.5
0.6
0.7
VREF + 0.2
VREF – 0.2
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
HSTL I
3.3
3.3
2.5
–8 mA
V
CCIO – 1.1V
8 mA
VREF + 0.2 VCCIO + 0.3 –0.3V VREF – 0.2
VREF + 0.2 VCCIO + 0.3 –0.3V VREF – 0.2
VREF + 0.18 VCCIO + 0.3 –0.3V VREF – 0.18
VREF + 0.18 VCCIO + 0.3 –0.3V VREF – 0.18
VREF + 0.1 VCCIO + 0.3 –0.3V VREF – 0.1
VREF + 0.1 VCCIO + 0.3 –0.3V VREF – 0.1
VREF + 0.1 VCCIO + 0.3 –0.3V VREF – 0.1
VREF + 0.1 VCCIO + 0.3 –0.3V VREF – 0.1
1.5
–16 mA VCCIO – 0.9V 16 mA
–7.6 mA CCIO – 0.62V 7.6 mA
0.5
1.25
1.25
0.75
0.75
0.9
V
0.54
0.35
0.4
2.5 –15.2 mA VCCIO – 0.43V 15.2 mA
1.5
1.5
1.5
1.5
–8 mA
VCCIO – 0.4V
8 mA
HSTL II
HSTL III
HSTL IV
–16 mA VCCIO – 0.4V 16 mA
0.4
–8 mA
–8 mA
V
CCIO – 0.4V 24 mA
0.4
0.9
VCCIO – 0.4V 48 mA
0.4
Configuration Parameters
Parameter
tRECONFIG
Description
Min.
Unit
Reconfig pin LOW time before it goes HIGH
200
ns
• VCC pins can be powered up in any order. This includes
VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL and VCCPRG
• All VCCIOs on a bank should be tied to the same potential
and powered up together.
• All VCCIOs (even the unused banks) need to be powered up
to at least 1.5V before configuration has completed.
• Maximum ramp time for all VCCs should be 0V to nominal
voltage in 100 ms.
Power-up Sequence Requirements
• Upon power-up, all the outputs remain three-stated until all
the VCC pins have powered-up to the nominal voltage and
the part has completed configuration.
• The part will not start configuration until VCC, VCCIO
VCCJTAG, VCCCNFG, VCCPLL and VCCPRG have reached
nominal voltage.
.
,
Notes:
9. PCI spec (rev 2.2) requires the IDSEL pin to have capacitance less than or equal to 8 pF. Delta39K Pin Tables starting from page 45, identify all the I/O pins in
a given package, which can be used as IDSEL in a PCI design. All other I/O pins meet the PCI requirement of capacitance less than or equal to 10 pf.
10. The number of I/Os which can be used in each I/O bank depends on the type of I/O standards and the number of VCCIO and GND pins being used. Please refer
to the application note titled “Delta39K and Quantum38K I/O Standards and Configurations” for details.
•
•
The source current limit per I/O bank per Vccio pin is 165 mA.
The sink current limit per I/O bank per GND pin is 230 mA.
11. See “Power-up Sequence Requirements” below for VCCIO requirement.
12. 25W resistor terminated to termination voltage of 1.5V.
Document #: 38-03039 Rev. *H
Page 17 of 86
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