Delta39K™ ISR™
CPLD Family
CompactPCI Hot Swap
output (from corner to corner on the device), incurs a worst-
case delay in the 39K100 regardless of the amount of logic or
which horizontal and vertical channels are used. This is the tPD
shown in Figure 10. For synchronous systems, the input set-
up time to the output macrocell register and the clock to output
time are shown as the parameters tMCS and tMCCO shown in
the Figure 10. These measurements are for any output and
synchronous clock, regardless of the logic placement.
The CompactPCI Hot Swap specification allows the removal
and insertion of cards into CompactPCI sockets without
switching-off the bus. Delta39K CPLDs can be used as a
CompactPCI host or target on these cards.
This feature is useful in telecommunication and networking
applications as it allows implementation of high availability
systems, where repairs and upgrades can be done without
downtime.
The Delta39K features:
• no dedicated vs. I/O pin delays
• no penalty for using 0 – 16 product terms
• no added delay for steering product terms
• no added delay for sharing product terms
• no output bypass delays.
Delta39K CPLDs are CompactPCI Hot Swap Ready per
CompactPCI Hot Swap specification R2.0, with the following
exception:
• The I/O cells do not provide bias voltage support. External
resistors can be used to achieve this, per section 3.1.3.1 of
the CompactPCI Hot Swap specification R2.0. A simple
board level solution is provided in the application note titled
“Hot-Swapping Delta39K and Quantum38K CPLDs.”
The simple timing model of the Delta39K family eliminates
unexpected performance penalties.
Family, Package, and Density Migration in Delta39K
CPLDs
Timing Model
One important feature of the Delta39K family is the simplicity
of its timing. All combinatorial and registered/synchronous
delays are worst case and system performance is static (as
shown in the AC specs section) as long as data is routed
through the same horizontal and vertical channels. Figure 10
illustrates the true timing model for the 200-MHz devices. For
synchronous clocking of macrocells, a delay is incurred from
macrocell clock to macrocell clock of separate Logic Blocks
within the same cluster, as well as separate Logic Blocks
within different clusters. This is respectively shown as tSCS and
tSCS2 in Figure 10. For combinatorial paths, any input to any
The Delta39K CPLDs combine dense logic, embedded mem-
ory and configurable I/O standards. Further design flexibility is
added by the easy migration options available between differ-
ent packages and densities of Delta39K CPLD offerings.
This migration flexibility makes changes or additions to
designs simple even after PCB layout. It also provides the
ability for experimental designs to be used on production
PCBs. Please refer to the application note titled “Family,
Package, and Density Migration in Delta39K CPLDs.”
Document #: 38-03039 Rev. *H
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