Delta39K™ ISR™
CPLD Family
Table 6 describes the valid phase shift options that can be
For more details on the architecture and operation of this PLL
please refer to the application note entitled “Delta39K PLL and
Clock Tree”.
used with or without an external feedback.
Table 7 is an example of the effect of all the available divide
and phase shift options on a VCO output of 250 MHz. It also
shows the effect of division on the duty cycle of the resultant
clock. Note that the duty cycle is 50-50 when a VCO output is
divided by an even number. Also note that the phase shift
applies to the VCO output and not to the divided output.
Table 4. Valid PLL Multiply and Divide Options—without External Feedback
Valid Multiply Options
Input Frequency
Valid Divide Options
Output Frequency (INTCLK[3:0]) Off-chip Clock
(GCLK[0])
fPLLI (MHz)
VCO Output
Value Frequency (MHz)
Value
fPLLO (MHz)
DC–12.5
6.25–133
6.25–266
6.25–266
6.25–266
6.25–266
6.25–266
6.25–266
6.25–266
Frequency
DC–12.5
N/A
1
N/A
N/A
DC–6.25
100–133
50–133
100–133
100–266
100–266
100–266
100–266
100–266
100–266
200–266
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
3.125–66
3.125–133
3.1–266
2
33.3–88.7
25–66
3
4
3.125–133
3.1–133
20–53.2
16.6–44.3
12.5–33
12.5–16.625
5
6
3.1–133
8
3.125–133
3.125–133
16
Table 5. Valid PLL Multiply and Divide Options—With External Feedback
Valid Multiply Options
Valid Divide Options
Input (GCLK) Frequency
fPLLI (MHz)
VCO Output
Frequency (MHz)
Output (INTCLK) Frequency
fPLLO (MHz)
Off-chip Clock
Frequency
Value
Value
50–133
1
1
1
1
1
1
1
100–266
100–266
100–266
100–266
125–266
150–266
200–266
1
2
3
4
5
6
8
100–266
50–133
25–66.5
50–133
25–66.5
16.67–44.33
12.5–33.25
12.5–26.6
12.5–22.17
12.5–16.63
33.33–88.66
25–66.5
16.67–44.33
12.5–33.25
12.5–26.6
12.5–22.17
12.5–16.63
25–53.2
25–44.34
25–33.25
Table 6. Recommended PLL Phase Shift Options
Without External Feedback
With External Feedback
0°,45°, 90°, 135°, 180°, 225°, 270°, 315°
0°
Table 7. Timing of Clock Phases for all Divide Options for a VCO Output Frequency of 250 MHz
Divide
Factor
Period
(ns)
0°
(ns)
45°
(ns)
90°
(ns)
135°
(ns)
180°
(ns)
225°
(ns)
270°
(ns)
315°
(ns)
Duty Cycle%
1
2
4
40–60
50
0
0
0
0
0
0
0
0
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
8
3
12
16
20
24
32
64
33–67
50
4
5
40–60
50
6
8
50
16
50
Document #: 38-03039 Rev. *H
Page 12 of 86
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