Delta39K™ ISR™
CPLD Family
Switching Characteristics — Parameter Descriptions Over the Operating Range[13] (continued)
Parameter
Description
Delay from the clock pin to the input of the clock driver
tCKIN
tIOREGPIN Delay from the I/O pin to the input of the I/O register
PLL Parameters
tMCCJ
Maximum cycle to cycle jitter time
PLL zero phase delay with clock tree deskewed
PLL zero phase delay without clock tree deskewed
Lock time for the PLL
tDWSA
tDWOSA
tLOCK
tINDUTY
fPLLI
Input duty cycle
Input frequency of the PLL
fPLLO
Output frequency of the PLL
fPLLVCO
PSAPLLI
fMPLLI
PLL VCO frequency of operation
Percentage modulation allowed (spread awareness) on the PLL input clock
Frequency of modulation allowed on PLL input clock. This specifies how fast the fPLLI sweeps between fPLLI
(1–PSAPLLI/100) and fPLLI* (1+ PSAPLLI/100)
*
JTAG Parameters
tJCKH
tJCKL
tJCP
tJSU
tJH
TCLK HIGH time
TCLK LOW time
TCLK clock period
JTAG port set-up time (TDI/TMS inputs)
JTAG port hold time (TDI/TMS inputs)
JTAG port clock to output time (TDO)
JTAG port valid output to high impedance (TDO)
JTAG port high impedance to valid output (TDO)
tJCO
tJXZ
tJZX
Cluster Memory Timing Parameter Descriptions Over the Operating Range
Parameter
Description
Asynchronous Mode Parameters
tCLMAA
tCLMPWE
tCLMSA
tCLMHA
tCLMSD
tCLMHD
Cluster memory access time. Delay from address change to Read data out
Write Enable pulse width
Address set-up to the beginning of Write Enable with both signals from the same I/O block
Address hold after the end of Write Enable with both signals from the same I/O block
Data set-up to the end of Write Enable
Data hold after the end of Write Enable
Synchronous Mode Parameters
tCLMCYC1
ClockcycletimeforflowthroughReadandWriteoperations (frommacrocellregister throughclustermemory
back to a macrocell register in the same cluster)
tCLMCYC2
Clock cycle time for pipelined Read and Write operations (from cluster memory input register through the
memory to cluster memory output register)
tCLMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
Address, data, and WE hold time of pin inputs, relative to a global clock
Global clock to data valid on output pins for flow through data
Global clock to data valid on output pins for pipelined data
tCLMH
tCLMDV1
tCLMDV2
tCLMMACS1
tCLMMACS2
tMACCLMS1
Cluster memory input clock to macrocell clock in the same cluster
Cluster memory output clock to macrocell clock in the same cluster
Macrocell clock to cluster memory input clock in the same cluster
Document #: 38-03039 Rev. *H
Page 19 of 86
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