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39K165 参数 Datasheet PDF下载

39K165图片预览
型号: 39K165
PDF下载: 下载PDF文件 查看货源
内容描述: CPLD器件的FPGA DensitiesTM [CPLDs at FPGA DensitiesTM]
分类和应用:
文件页数/大小: 86 页 / 1209 K
品牌: CYPRESS [ CYPRESS ]
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Delta39K™ ISR™  
CPLD Family  
Junction Temperature...................................................135°C  
Maximum Ratings  
V
V
CC to Ground Potential...................................0.5V to 4.6V  
CCIO to Ground Potential................................0.5V to 4.6V  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Storage Temperature  
(39K200, 208 EQFP) .................................45°C to +125°C  
Storage Temperature  
(all other densities and packages) ..............65°C to +150°C  
Soldering Temperature................................................. 220°C  
Ambient Temperature with  
Power Applied...............................................40°C to +85°C  
DC Voltage Applied to Outputs  
in High-Z state..................................................0.5V to 4.5V  
DC Input voltage...............................................–0.5V to 4.5V  
DC Current into Outputs........................................ ± 20 mA[6]  
Static Discharge Voltage  
(per JEDEC EIA./JESD22–A114A)............................ >2001V  
Latch-up Current ..................................................... >200 mA  
Operating Range  
Ambient  
Temperature  
Junction  
Temperature  
Output  
Condition  
VCCJTAG  
/
Range  
VCCIO  
VCC  
VCCCNFG VCCPLL VCCPRG  
Commercial  
0°C to +70°C  
0°C to +85°C  
3.3V  
2.5V  
1.8V  
1.5V  
3.3V  
2.5V  
1.8V  
1.5V  
3.3V ± 0.3V 3.3V±0.3Vor Same as Sameas 3.3V ±  
2.5V ± 0.2V  
(39KV)  
VCCIO  
VCC  
0.3V  
2.5V ± 0.2V  
1.8V ± 0.15V  
1.5V ± 0.1V[5]  
3.3V ± 0.3V  
2.5V ± 0.2V  
1.8V ± 0.15V  
1.5V ± 0.1V[5]  
Industrial  
–40°C to +85°C –40°C to +100°C  
DC Characteristics  
VCCIO = 3.3V VCCIO = 2.5V  
VCCIO = 1.8V  
Test  
Conditions  
Parameter  
Description  
Min. Max. Min. Max. Min.  
Max.  
Unit  
VDRINT  
Data Retention VCC Voltage  
(config data may be lost below this)  
1.5  
1.5  
1.5  
V
VDRIO  
Data Retention VCCIO Voltage  
(config data may be lost below this)  
1.2  
1.2  
1.2  
V
[7]  
IIX  
Input Leakage Current  
Output Leakage Current  
GND VI 3.6V  
–10  
–10  
10  
10  
–10  
–10  
10  
10  
–10  
–10  
10  
10  
µA  
µA  
IOZ  
GND VO ≤  
VCCIO  
[8]  
IOS  
Output Short Circuit Current  
VCCIO = Max.  
VOUT = 0.5V  
–160  
–160  
–160  
µA  
µA  
µA  
IBHL  
IBHH  
Input Bus Hold LOW Sustaining Current VCC = Min.  
VPIN = VIL  
+40  
–40  
+30  
–30  
+25  
–25  
Input Bus Hold HIGH Sustaining Current VCC = Min.  
VPIN = VIH  
IBHLO  
IBHHO  
ICC0  
Input Bus Hold LOW Overdrive Current VCC = Max.  
Input Bus Hold HIGH Overdrive Current VCC = Max.  
+250  
–250  
All bins  
20  
20  
30  
60  
60  
+200  
–200  
All bins  
20  
20  
30  
60  
60  
+150  
µA  
µA  
µA  
–150  
–125 bin –83 bin  
Standby Current  
39K30  
3
3
5
12  
12  
20  
40  
40  
39K50  
39K100  
39K165  
39K200  
10  
10  
Note:  
6. DC current into outputs is 36 mA with HSTL III, 48 mA with HSTL IV, and 36 mA with GTL+ (with 25W pull-up resistor and VTT = 1.5).  
7. Input Leakage current is ±10µA for all the pins on all the Delta39K package except the following pins in Delta39K100 packages: The input leakage current spec  
for these pins in ±200µA  
Delta39K100  
Package  
388-BGA  
484-FBGA  
676-FBGA  
Pins  
B4, C2  
B8, G9  
F11, J11  
8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test  
problems caused by tester-ground degradation. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-03039 Rev. *H  
Page 16 of 86  
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