Delta39K™ ISR™
CPLD Family
Switching Characteristics — Parameter Values Over the Operating Range (continued)
125
83
233
200
181
Parameter
tINDUTY
Min.
40
Max.
60
Min.
40
Max.
60
Min.
40
Max.
60
Min.
40
Max.
60
Min.
40
Max.
60
Unit
%
[14]
fPLLO
6.2
266
133
266
+0.3
50
6.2
266
133
266
+0.3
50
6.2
266
133
266
+0.3
50
6.2
200
100
266
+0.3
50
6.2
200
100
266
+0.3
50
MHz
MHz
MHz
%
[14]
fPLLI
12.5
100
–0.3
12.5
100
–0.3
12.5
100
–0.3
12.5
100
–0.3
12.5
100
–0.3
fPLLVCO
PSAPLLI
fMPLLI
KHz
JTAG Parameters
tJCKH
tJCKL
tJCP
tJSU
tJH
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
ns
ns
ns
ns
ns
ns
ns
ns
tJCO
tJXZ
tJZX
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
Input and Output Standard Timing Delay
Adjustments
All the timing specifications in this data sheet are specified
based on LVCMOS compliant inputs and outputs (fast slew
rates).[15] Apply following adjustments if the inputs and outputs
are configured to operate at other standards.
Output Delay Adjustments
Slow Slew Rate
Fast Slew Rate
(additional delay to fast slew rate)
tIODSLOW tEASLOW tERSLOW tIOIN
2.6
Input Delay Adjustments
tCKIN tIOREGPIN
0
I/O Standard
LVTTL – 2 mA
LVTTL – 4 mA
LVTTL – 6 mA
LVTTL – 8 mA
LVTTL – 12 mA
LVTTL – 16 mA
LVTTL – 24 mA
LVCMOS
tIOD
2.75
tEA tER
0
0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
0
0
0
0
1.8
1.8
0
0
0
2.5
0
0
2.5
0
0
0
1.2
0
0
2.4
0
0
0
0.6
0
0
2.3
0
0
0
0.16
0
0
0
2.0
0
0
0
0
0
0
1.6
0
0
0
0
0
2.0
0
0
0
LVCMOS3
0.14
0.41
1.6
0.05
0.1
0.7
0
0
2.0
0.1
0.2
0.5
0
0.1
0.2
0.4
0
0.2
0.4
0.3
0
LVCMOS2
0
2.0
LVCMOS18
3.3V PCI
0.1
2.1
–0.14
0
2.0
GTL+
0.02[16] 0.6[16]
0.9[16]
0.1
0
2.0
0.5
0.5
0.5
0.4
0.3
0.3
0.2
0.3
0.3
SSTL3 I
–0.15
–0.4
0.3
0.2
2.0
SSTL3 II
2.0
Notes:
14. Refer to page 11 and the application note titled “Delta39K PLL and Clock Tree” for details on the PLL operation.
15. For “slow slew rate” output delay adjustments, refer to Warp software’s static timing analyzer results.
16. These delays are based on falling edge output. The rising edge delay depends on the size of pull-up resistor and termination voltage.
Document #: 38-03039 Rev. *H
Page 22 of 86
CYPRESS [ CYPRESS ]
