CPLL66-4160-4380
0.60" SQ SMD
Table II. Latch Summary
REFERENCE COUNTER LATCH
ANTI-
BACKLASH
WIDTH
TEST
CONTROL
BITS
RESERVED
14-BIT REFERENCE COUNTER
MODE BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9
DB9
R8
DB8
R7
DB7
R6
DB6
R5
DB5
R4
DB4
R3
DB3
R2
DB2
R1
DB1
DB0
X
0
0
C2 (0) C1 (0)
N COUNTER LATCH
CONTROL
BITS
RESERVED
13-BIT B COUNTER
6-BIT A COUNTER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
B2
DB8
B1
DB7
A6
DB6
A5
DB5
A4
DB4
A3
DB3
A2
DB2
A1
DB1
DB0
G1
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
C2 (0) C1 (1)
FUNCTION LATCH
CURRENT
SETTING
2
CURRENT
SETTING
1
PRESCALER
VALUE
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
F4
DB8
F3
DB7
F2
DB6
M3
DB5
M2
DB4
M1
DB3
PD1
DB2
F1
DB1
DB0
P2
P1
PD2
CP16
CP15
CP14
CP13
CP12
CP11
TC4
TC3
TC2
TC1
F5
C2 (1) C1 (0)
INITIALIZATION LATCH
CURRENT
SETTING
2
CURRENT
SETTING
1
PRESCALER
VALUE
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P2 P1 PD2 CP16 CP15 CP14 CP13 CP12 CP11 TC4 TC3 TC2 TC1 F5
DB9
F4
DB8
F3
DB7
F2
DB6
M3
DB5
M2
DB4
M1
DB3
PD1
DB2
F1
DB1
DB0
C2 (1) C1 (1)
When using the CPLL66 family in a synthesizer application, all four 24 bit registers need to
be written into after power-up. After writing all four latches the first time, subsequent
frequency step changes can be accomplished by changing the N Counter Latch only.
Page 5 of 6
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