4.0 Registers
RS8953B/8953SPB
4.17 PRA Receive Read
HDSL Channel Unit
E_MODE
Controls the behavior of the E-bits transmitted towards the HDSL link, as follows:
Code
00
01
E-bits
Transparent
From Bits Buffer 0
Automatic
10
11
Illegal
The Automatic mode works in conjunction with the transmitter CRC4 check result
(reported also in TX_PRA_MON0), as follows:
Receiver CRC Check
E-bits Forced to:
Error
OK
0
1
NOTE:
The value of this register takes effect starting with the next PCM multiframe
following the write access cycle completion.
0x81—PRA Receive Control Register 1 (RX_PRA_CTRL1)
7
6
5
4
3
2
1
0
RESET_CRC_CNT RESET_E_CNT
AIS
A_MODE
CRC4_MODE[1:0]
SYNCHR_EN
PRA_EN
PRA_EN
Used to enable or globally disable the transmit PRA circuitry, as follows:
0 = Disable ALL TX PRA functionality
1 = Enable ALL TX PRA functionality
SYNCHR_EN
Used to enable or disable the PCM multiframe synchronization state machine, as follows:
0 = Enable synchronization and force HUNT mode. Take RMSYNC as
indicator of frame.
1 = Disable synchronization. Take RMSYNC as multiframe indicator.
CRC4_MODE
Controls the behavior of the CRC bits, transmitted towards the PCM link, as follows:
Code
00
01
E-bits
Transparent
All 1
10
11
Re-calculated
Illegal
A_MODE
AIS
Controls the behavior of A-bits, transmitted towards the PCM link, as follows:
0 = Transparent
1 = From bits buffer 0
Enables to override all 32 slots of an PCM frame except slot 0, transmitted towards the PCM
link with a constant pattern:
0 = Disable (Normal)
1 = 0xFF
NOTE:
AIS enables to achieve framed AIS. To achieve unframed arbitrary AUX pattern
generation, use the existing feature of the channel unit.
4-74
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
