RS8953B/8953SPB
4.0 Registers
HDSL Channel Unit
4.18 PRA Receive Write
4.18 PRA Receive Write
Table 4-15. PRA Receive Write Registers
Address
Register Label
Bits
Name/Description
0xB0
0xB1
0xB2
0xB4
RX_PRA_CTRL0
RX_PRA_CTRL1
RX_BITS_BUFF1
RX_PRA_BUFF0
7
8
6
8
PRA Receive Read Register 0
PRA Receive Control Register 1
PRA Receive Bits Buffer 1
PRA Receive Bit Counter
0xB0—PRA Receive Control Register 0 (RX_PRA_CTRL0)
7
6
5
4
3
2
1
0
E_MODE[1:0]
SA8_MODE
SA7_MODE
—
SA6_MODE
SA5_MODE
SA4_MODE
SA4_MODE
SA5_MODE
SA6_MODE
SA7_MODE
SA8_MODE
E_MODE
Controls the behavior of Sa4 bits transmitted towards PCM, as follows:
0 = Transparent
1 = From bits buffer 1
Controls the behavior of Sa5 bits transmitted towards PCM, as follows:
0 = Transparent
1 = From bits buffer 0
Controls the behavior of Sa6 bits transmitted towards PCM, as follows:
0 = Transparent
1 = From bits buffer 0
Controls the behavior of Sa7 bits transmitted towards PCM, as follows:
0 = Transparent
1 = From bits buffer 1
Controls the behavior of Sa8 bits transmitted towards PCM, as follows:
0 = Transparent
1 = From bits buffer 1
Controls the behavior of the E-bits transmitted towards the HDSL link, as follows:
Code
00
01
E-bits
Transparent
From bits buffer 0
Automatic
10
11
Illegal
N8953BDSB
Conexant
4-77
CONEXANT [ CONEXANT SYSTEMS, INC ]
