4.0 Registers
RS8953B/8953SPB
4.16 PRA Transmit Write
HDSL Channel Unit
When this assumption is not valid, this register may be used to internally reposition the TMSYNC to coincide
with Bit 0.
0x74—PRA Transmit Bits Buffer 0 (TX_BITS_BUFF0)
7
6
5
4
3
2
1
0
Sa _4
Sa _3
Sa _2
Sa _1
Sa
A
E2
E1
6
6
6
6
5
The value of this register is only relevant if the corresponding MODE bit of TX_PRA_CTRL0 is set. A new
written value takes effect starting with the next PCM multiframe following the register write access cycle
completion. Each bit of this register is used in the odd frames of the PCM multiframe.
E1
E2
A
The new value to be inserted into the E1 location of the data stream, in the PCM to HDSL
direction. E1 is used in Frame 13.
The new value to be inserted into the E2 location of the data stream, in the PCM to HDSL
direction. E2 is used in Frame 15.
The new value to be inserted into the A-bit location of the data stream, in the PCM to HDSL
direction. A-bit is used in all odd frames.
Sa
The new value to be inserted into the Sa location of the data stream, in the PCM to HDSL
5
5
direction. Sa is used in all odd frames.
5
Sa _1, _2, _3, _4 The new value to be inserted into the Sa _1, _2, _3, _4 location of the data stream, in the PCM
6
6
to HDSL direction. Sa _1 is used in Frames 1 and 9. Sa _2 is used in Frames 3 and 11. Sa _3
6
6
6
is used in Frames 5 and 13. Sa _4 is used in Frames 7 and 15.
6
4-72
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
