4.0 Registers
RS8953B/8953SPB
4.15 PRA Transmit Read
HDSL Channel Unit
This register is updated once every PCM multiframe. The bits in this register correspond to the bits in the
transmitted PCM multiframe stream, in the PCM to HDSL direction.
Sa6 _1, _2, _3, _4 Sa6 _1, _2, _3, _4 is updated only if detected identical in the last 8 submultiframes, given that
the respective field was not masked in TX_BITS_BUF1.
Sa5
A
Sa5 is only updated only if detected identical in the last 8 submultiframes, given that the
respective field was not masked in TX_BITS_BUF1.
A-bit is only updated only if detected identical in the last 8 submultiframes, given that the
respective field was not masked in TX_BITS_BUF1.
0x46—PRA Transmit Monitor Register 0 (TX_PRA_MON0)
7
6
5
4
3
2
1
0
Sa
Sa
Sa
SYNCH_STATE
—
—
CRC error2
CRC error1
8
7
4
CRC error 1
Represents the CRC check result in submultiframe 1.
Represents the CRC check result in submultiframe 2.
CRC error 2
Sa , Sa , and Sa
8
Updated with a value that represents the majority over the eight off-frames.
Represents the status of the multiframe synchronization machine.
4
7
SYNCH_STATE
0 = Not synchronized
1 = Synchronized
If SYNCH_STATE is 1, the relative frame with which synchronization was achieved in
TX_PRA_MON2 is readable.
0x47—PRA Transmit Monitor Register 2 (TX_PRA_MON2)
7
6
5
4
3
2
1
0
—
—
—
—
TX_PRA_MON2[3:0]
The 4 bits of this register represent the original number of the relative frame with which synchronization was
achieved. This is relevant only if bit SYNCH_STATE of TX_PRA_MON0 reads 1.
4-68
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
