CX82100 Home Network Processor Data Sheet
9
General Purpose Input/Output Interface Description............................................................................ 9-1
9.1
9.2
9.3
GPIO Pin Description...................................................................................................................................................9-1
GPIO Register Memory Map........................................................................................................................................9-2
GPIO Registers............................................................................................................................................................9-3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
GPIO Option Register for GPIO[39:37; 32] (GPIO_OPT: 0x003500B0) ........................................................9-3
GPIO Output Enable Register 1 for GPIO[15:14; 8:5] (GPIO_OE1: 0x003500B4) .........................................9-4
GPIO Output Enable Register 2 for GPIO[31; 27:16] (GPIO_OE2: 0x003500B8) ..........................................9-4
GPIO Output Enable Register 3 for GPIO[39:37; 32] (GPIO_OE3: 0x003500BC)..........................................9-5
GPIO Data Input Register 1 for GPIO[15:14; 8:5] (GPIO_DATA_IN1: 0x003500C0).....................................9-5
GPIO Data Input Register 2 for GPIO[31; 27:24; 22:16] (GPIO_DATA_IN2: 0x003500C4) ...........................9-6
GPIO Data Input Register 3 for GPIO[39:37; 32] (GPIO_DATA_IN3: 0x003500C8)......................................9-6
GPIO Data Output Register 1 for GPIO[15:14; 8:5] (GPIO_DATA_OUT1: 0x003500CC) ...............................9-7
GPIO Data Output Register 2 for GPIO[31; 27:24; 22:16] (GPIO_DATA_OUT2: 0x003500D0) .....................9-8
9.3.10 GPIO Data Output Register 3 for GPIO[39:37; 32] (GPIO_DATA_OUT3: 0x003500D4) ................................9-9
9.3.11 GPIO Interrupt Status Register 1 for GPIO[15:14; 8:5] (GPIO_ISR1: 0x003500D8)...................................9-10
9.3.12
GPIO Interrupt Status Register 2 for GPIO[31; 27:24; 22:16] (GPIO_ISR2: 0x003500DC).........................9-10
9.3.13 GPIO Interrupt Status Register 3 for GPIO[39:37; 32] (GPIO_ISR3: 0x003500E0).....................................9-12
9.3.14 GPIO Interrupt Enable Register 1 for GPIO[15:14; 8:5] (GPIO_IER1: 0x003500E4) ...................................9-13
9.3.15 GPIO Interrupt Enable Register 2 for GPIO[31; 27:24; 22:16] (GPIO_IER2: 0x003500E8) .........................9-14
9.3.16 GPIO Interrupt Enable Register 3 for GPIO[39:37; 32] (GPIO_IER3: 0x003500EC)....................................9-15
9.3.17 GPIO Interrupt Polarity Control Register 1 for GPIO[15:14; 8:5] (GPIO_IPC1: 0x003500F0)......................9-16
9.3.18 GPIO Interrupt Polarity Control Register 2 for GPIO[31; 27:24; 22:16] (GPIO_IPC2: 0x003500F4)............9-17
9.3.19 GPIO Interrupt Polarity Control Register 3 for GPIO[39:37; 32] (GPIO_IPC3: 0x003500F8).......................9-18
9.3.20 GPIO Interrupt Sensitivity Mode Register 1 for GPIO[15:14; 8:5] (GPIO_ISM1: 0x003500A0)...................9-19
9.3.21 GPIO Interrupt Sensitivity Mode Register 2 for GPIO[31; 27:24; 22:16] (GPIO_ISM2: 0x003500A4).........9-20
9.3.22 GPIO Interrupt Sensitivity Mode Register 3 for GPIO[39:37; 32] (GPIO_ISM3: 0x003500A8)....................9-21
10 Memory to Memory Transfer Input/Output........................................................................................ 10-1
10.1 Operation ..................................................................................................................................................................10-1
10.2 M2M Register Memory Map......................................................................................................................................10-3
10.3 M2M Registers..........................................................................................................................................................10-3
10.3.1 Memory to Memory DMA Data Register (M2M_DMA: 0x00350000) .........................................................10-3
10.3.2 Memory to Memory DMA Transfer Control/Counter (M2M_Cntl: 0x00350004).........................................10-3
11 Interrupt Controller Interface Description .......................................................................................... 11-1
11.1 INTC Register Memory Map ......................................................................................................................................11-1
11.2 INTC Registers ..........................................................................................................................................................11-1
11.2.1 Interrupt Level Assignment Register (INT_LA: 0x00350040).....................................................................11-1
11.2.2 Interrupt Status Register (INT_Stat: 0x00350044).....................................................................................11-2
11.2.3 Interrupt Set Status Register (INT_SetStat: 0x00350048)..........................................................................11-4
11.2.4 Interrupt Mask Register (INT_Msk: 0x0035004C)......................................................................................11-4
11.2.5 Interrupt Mask Status Register (INT_Mstat: 0x00350090).........................................................................11-4
12 Timers Interface Description.............................................................................................................. 12-1
12.1 Programmable Periodic Timers.................................................................................................................................12-1
12.2 Watchdog Timer........................................................................................................................................................12-1
12.3 Timer Usage/SDRAM Refresh with Other Frequencies...............................................................................................12-2
12.4 Timer Registers Memory Map ...................................................................................................................................12-3
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