CX82100 Home Network Processor Data Sheet
7
Ethernet Media Access Control Interface Description .......................................................................... 7-1
7.1
7.2
7.3
7.4
7.5
7.6
7.7
MAC Frame Format .....................................................................................................................................................7-2
Parameterized Values Used in Implementation............................................................................................................7-3
EMAC Functional Features...........................................................................................................................................7-4
EMAC Architecture ......................................................................................................................................................7-6
Media Independent Interface (MII) ..............................................................................................................................7-7
EMAC Interrupts..........................................................................................................................................................7-8
TMAC Architecture ......................................................................................................................................................7-9
7.7.1
7.7.2
7.7.3
7.7.4
Transmit Frame Structure............................................................................................................................7-9
Transmit Descriptor...................................................................................................................................7-11
Transmit Status (TSTAT) ...........................................................................................................................7-12
Sequence of Transmitter DMA Operation...................................................................................................7-14
7.8
RMAC Architecture....................................................................................................................................................7-15
7.8.1
Support for the Detection of Invalid MAC Frames ......................................................................................7-15
Condition 1........................................................................................................................................7-15
Condition 2........................................................................................................................................7-15
Condition 3........................................................................................................................................7-15
Support for the Reception Without Contention ..........................................................................................7-15
Support for the Reception With Contention ...............................................................................................7-16
Address Filtering........................................................................................................................................7-16
Setup Frame ......................................................................................................................................7-16
Perfect Address Filtering....................................................................................................................7-16
Example of a Perfect Address Filtering Setup Frame ..........................................................................7-17
Imperfect Address Filtering................................................................................................................7-18
Example of an Imperfect Address Filtering Setup Frame ....................................................................7-20
Address Filtering Modes ....................................................................................................................7-22
Receive Status Handling............................................................................................................................7-23
Sequence of Receiver DMA Operation .......................................................................................................7-26
7.8.2
7.8.3
7.8.4
7.8.5
7.8.6
7.9
7-Wire Serial Interface (7-WS) ..................................................................................................................................7-27
7.10 EMAC Register Memory Map ....................................................................................................................................7-28
7.11 EMAC Registers ........................................................................................................................................................7-29
7.11.1 EMAC x Source/Destination DMA Data Register (E_DMA_1: 0x00310000 and E_DMA_2:
0x00320000).............................................................................................................................................7-29
7.11.2 EMAC x Destination DMA Data Register (ET_DMA_1: 0x00310020 and ET_DMA_2: 0x00320020)...........7-29
7.11.3 EMAC x Network Access Register (E_NA_1: 0x00310004 and E_NA_2: 0x00320004) ..............................7-30
7.11.4 EMAC x Status Register (E_Stat_1: 0x00310008 and E_Stat_2: 0x00320008) ..........................................7-33
7.11.5 EMAC x Receiver Last Packet Register (E_LP_1: 0x00310010 and E_LP_2: 0x00320010)........................7-34
7.11.6 EMAC x Interrupt Enable Register (E_IE_1: 0x0031000C and E_IE_2: 0x0032000C).................................7-35
7.11.7 EMAC x MII Management Interface Register (E_MII_1: 0x00310018 and E_MII_2: 0x00320018).............7-36
8
USB Interface Description.................................................................................................................... 8-1
8.1
UDC Data Path ............................................................................................................................................................8-3
8.1.1
8.1.2
USB Transmit Data Path (Endpoint IN Channel)...........................................................................................8-3
USB Receive Data Path (Endpoint OUT Channel) .........................................................................................8-4
8.2
USB Data Flow ............................................................................................................................................................8-5
vi
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