CX82100 Home Network Processor Data Sheet
2.4
Interface Timing and Waveforms
2.4.1
External Memory Interface (SDRAM)
The External Memory Interface provides a PC100-compatible SDRAM interface. Signal
interface timing is summarized in Figure 2-5.
Note that MCLK is derived from the BCLK PLL output (see Section 12). Accordingly,
there is no fixed relationship between the HNP clock input (CLKI pin) and the External
Memory Interface signals.
Figure 2-5. External Memory Interface Timing
10 ns min.
MCLK
1 ns min.
7.5 ns max.
MCKE, MA[11:0] MB[1:0], MM[1:0],
MCAS#, MRAS#, MWE#
MD[15:0] (to SDRAM)
4 ns min.
1 ns min.
MD[15:0] (from SDRAM)
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2.4.2
Host Interface Timing
The signal interface timing for the Host Interface is user programmable. By programming
the registers associated with the Host interface, desired timing characteristics such as
read/write pulse widths and setup and hold times can be established. For details regarding
Host Interface timing, refer to Section 5.1.5.
2.4.3
2.4.4
2.4.5
EMAC Interface Timing
To be added.
USB Interface Timing
To be added.
GPIO Interface Timing
The GPIO outputs are derived from the BCLK PLL output (see clocking chapter).
Accordingly, there is no fixed relationship between the HNP’s clock input (CLKI) and
the GPIO signals.
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Conexant Proprietary and Confidential Information
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CONEXANT [ CONEXANT SYSTEMS, INC ]
