CX82100 Home Network Processor Data Sheet
7.8.6
Sequence of Receiver DMA Operation
The sequence of receiver DMA operation is illustrated in Figure 7-11.
Figure 7-11. Sequence of Receiver DMA Operation
Host initiates the Setup Frame to
configure the H/W address filtering.
Transmit & receive operations are
disabled.
Host programs the type of address
filtering in the E_NA_1 or E_NA_2
register (7 different types).
Host specifies the circular buffer for
the receiving channel {x} by loading
the base pointer DMAC_{x}_Ptr1
and the length DMAC_{x}_Cnt1
Host controls the receive Start/Stop
by programming the E_NA_SR bit
of the E_NA_1 or E_NA_2 register
wait for
E_NA_SR
assertion
no
E_NA_SR=1?
yes
RMAC issues DMA_SAVE command to DMAC to
save DMAC_{x}_Cnt1 to DMAC_{x}_Cnt3
RMAC collects data bits from MII as
long as the Carrier Sense is aserted.
no
8 bytes of data
collected?
yes
RMAC issues DMA_XNXT to DMAC to
transfer the data to the buffer
no
A Complete frame
received?
yes
wait for
E_NA_SR
assertion
yes
E_NA_SR deasserted?
no
RMAC Updates the
MIB counters and
aborts the frame by
sending DMA_RELD
command to DMAC
no
A good frame received?
yes
MIB counter are loaded to the
status double-word which is in
turn written to the head of the
received frame by DMAC.
RMAC interrupts the host and the
host processes the good frame
RMAC resets MIB counters and
the status double-word.
101545_038
7-26
Conexant Proprietary and Confidential Information
101306C
CONEXANT [ CONEXANT SYSTEMS, INC ]
