CX82100 Home Network Processor Data Sheet
7.4
EMAC Architecture
Block diagram of the EMAC unit is shown in Figure 7-3.
Figure 7-3. EMAC Functional Block Diagram
ETXCK
ETXD[3:0]
TMAC
MAC
Transmitter
TXFIFO
Tx Buffer Manager
(TBM)
SYNC
DMA
APB
Interface
Rx Buffer Manager
(RBM)
SYNC
MAC
Receiver
RXFIFO
ERXD[3:0]
RMAC
HNP
ERXCK
101545_030
The EMAC module interfaces with the DMA controller through the DMA interface
block. The APB address is decoded in this block. Tx Buffer Manager (TBM) and Rx
Buffer Manager (RBM) blocks control the MAC Transmitter and MAC Receiver,
respectively. TBM and RBM issue the requests to the DMA controller and control their
own FIFOs.
Synchronization is required between the MAC receiver and the RBM because they
operate on different clocks (PCLK and EMx_RX_CLK, respectively). Similarly,
synchronization is required between the MAC transmitter and the TBM because they
operate on different clocks (PCLK and EMx_TX_CLK, respectively).
7-6
Conexant Proprietary and Confidential Information
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