CX82100 Home Network Processor Data Sheet
Full-duplex operation allows simultaneous transmission and reception of data, which can
effectively double data throughput to 20 or 200 Mb/s. In full-duplex mode, the HNP
starts transmitting a frame provided that IFG duration time has elapsed since its previous
transmission. Since there is no collision in full-duplex mode, the transmission always
ends successfully. The HNP monitors the line for a new frame transmission in both half
and full duplex modes. A new frame transmission is defined as both transmit data valid
and carrier sense asserted.
The following features of the EMAC should be taken into account:
•
The FCS is defined as a 32-bit field, which means the minimum number of data
bytes required for a meaningful FCS is 4 (i.e. you can not generate a 32-bit FCS
from data that is shorter than 32-bits). Packets which are less than 4 bytes long,
should not be checked for FCS.
•
Received EMAC frames are padded to align to qword boundaries, during
reception, prior to DMAC transfer. However, the length that is used in the length
status field is calculated prior to the padding insertion. This length field, FL, bits
31-16 of the RMAC in-line status qword, is provided in bytes. This length, FL,
includes the entire frame that was transmitted, including CRC, but it does not
include the padding bytes that were added by the EMAC receiver to align to the
qword boundary. The next frame is defined to start at the beginning of that same
qword boundary.
•
•
Setting up the EMAC receiver for address filtering is done by directly
programming all filter related register bits (E_NA_HP, E_NA_HO, E_NA_IF,
E_NA_PR, and E_NA_PM) via writes to the E_NA register.
If an RX FIFO overflow interrupt occurs, the RX should be reset via bit
E_NA_RRX in the E_NA register. The most recently written packet in the RX
circular buffer is damaged, and must be aborted by the software.
101306C
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