CX82100 Home Network Processor Data Sheet
7.6
EMAC Interrupts
The EMAC provides three interrupts each for EMAC1 and EMAC2:
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•
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Int_EMAC#{x}_ERR (diagnostics/exception interrupt)
Int_DMAC_EMAC#{x}_RX (packet received interrupt)
Int_DMAC_EMAC#{x}_TX (transmission complete interrupt)
where {x} indicates the EMAC number (1 or 2).
These interrupt bits are located in the INT_Stat register (see Section 11.2.2).
Int_EMAC#{x}_ERR is set to 1 if any number of EMAC interrupts occur. Before an
EMAC interrupt can be recognized by the HNP, its corresponding enable bit must be set
to 1 in E_IE_{x}. The equation for the Int_EMAC#{x}_ERR is as follows:
Int_EMAC#{x}_ERR =
(E_IE_AU and E_LP_AU) or
(E_IE_AI and (E_S_ES or E_S_TUF or E_S_TOF or E_S_RO or E_S_TJT or
E_S_RWT)) or
E_IE_NI and (E_LP_RI or E_LP_TI) or
(E_IE_TU and E_S_TU) or
(E_IE_RW and E_S_RWT) or
(E_IE_TOF and E_S_TOF) or
(E_IE_TUF and E_S_TUF) or
(E_IE_ED and E_S_ED) or
(E_IE_DF and E_S_DF) or
(E_IE_RLD and E_S_RLD) or
(E_IE_TF and E_S_TF) or
(E_IE_TJT and E_S_TJT) or
(E_IE_NCRS and E_S_NCRS) or
(E_IE_LCRS and E_S_LCRS) or
(E_IE_16 and E_S_16) or
(E_IE_LC and E_S_LC) or
(E_IE_RI and E_LP_RI) or
(E_IE_TI and E_LP_TI)
Int_DMAC_EMAC#{x}_RX bit field is set to 1 in the INT_Stat register after the
receiver posts the status in the status field of the RX buffer for a good packet when
E_NA_PB bit of E_NA_{x} is 0 (do not pass bad packet). When E_NA_PB is set to 1
(pass bad or good packet), The Int_DMAC_EMAC#{x}_RX bit is set after the receiver
post the status for a good or bad packet.
Int_DMAC_EMAC#{x}_TX bit field is set to 1 in the INT_Stat register after the
transmitter posts the status of the packet in the TX buffer or when the transmitter gets a
stop descriptor (ready bit in the TDES is zero).
7-8
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