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CX82100-42 参数 Datasheet PDF下载

CX82100-42图片预览
型号: CX82100-42
PDF下载: 下载PDF文件 查看货源
内容描述: 家庭网络处理器( HNP ) [Home Network Processor (HNP)]
分类和应用:
文件页数/大小: 226 页 / 1406 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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CX82100 Home Network Processor Data Sheet  
Revision History  
Changes Incorporated in Doc. No. 101306C  
1. Table 1-1: Revised Order No.  
2. Figure 2-3: Revised pin N13 to VSSO rather than VDDO for CX82100-41/-42.  
3. Figure 2-4: Revised pin N13 to VSSO rather than VDDO for CX82100-41/-42.  
4. Table 2-2: Revised pin N13 to VSSO rather than VDDO for CX82100-41/-42.  
5. Table 2-3: Revised pin N13 to VSSO rather than VDDO for CX82100-41/-42.  
6. Table 2-9: Revised GPIO20 to LAN 1 Reset (LAN1_RST#) rather than GPIO5.  
7. Table 2-10: Revised GPIO20 to LAN 1 Reset (LAN1_RST#) rather than GPIO5.  
Changes Incorporated in Doc. No. 101306B  
1. Chapter 1: Revised maximum MIPS, added HRDY# paragraph, and added CX82100  
HNP configuration differences to the introduction.  
2. Table 1-1: Added models numbers and expanded table.  
3. Section 1.5: Deleted.  
4. Section 2.1.1: Revised section with applicability to CX82100-11/-12/-51/-52.  
5. Section 2.1.2: Added section with applicability to CX82100-41/-42.  
6. Section 2.1.3: Added heading.  
7. Figure 2-1: Corrected pin number signals for M13 [HC08 (HRD#)], M12 [HC09  
(HWR#)], and P14 [HC00 (HCS0#)/GPIO32].  
8. Figure 2-1, Figure 2-2, and Table 2-1: Revised with applicability to CX82100-11/-  
12/-51/-52.  
9. Figure 2-3, Figure 2-4, and Table 2-2: Added with applicability to CX82100-41/-42.  
10. Table 2-3: Revised VSSO pins, revised USBP and USBN interface resistor value,  
HC00 pins, and HC10 pins, and GPIO17 and GPIO6 reset state.  
11. Section 2.3 (Old): Deleted.  
12. Figure 2-6: Corrected signal labels.  
13. Table 5-1: Rearranged.  
14. Section 5.1.5: Added reference to CX82100-11/-12/-51/-52.  
15. Section 5.1.6: Added new section applicable to CX82100-41/-42.  
16. Section 5.3.10: Added register description.  
17. Section 13.1: Added PLL_F 168 MHz maximum operating frequency.  
18. Table 13-3: Added PLL_F 168 MHz maximum operating frequency.  
19. Table 13-5: Added PLL_F 168 MHz maximum operating frequency.  
20. Section 13.4.1: Revised bits 25:24 (PLL_F_CR) description to add 84 MHz.  
21. Table 13-8: Added Example 6 for 168 MHz desired frequency.  
xiv  
Conexant Proprietary and Confidential Information  
101306C