CX82100 Home Network Processor Data Sheet
Table 7-9. 7-WS Interface Signals .................................................................................................................................7-27
Table 7-10. EMAC Registers..........................................................................................................................................7-28
Table 8-1. Endpoint Buffer Format in UDC Core...............................................................................................................8-6
Table 8-2. Example of the EndPtBuf Encoding.................................................................................................................8-7
Table 8-3. DMA Channel Supporting USB Receive OUT Endpoints ................................................................................8-10
Table 8-4. Status qword for Receive (OUT) Endpoint APB Buffers.................................................................................8-11
Table 8-5. DMA Channels for USB Transmit IN Endpoints .............................................................................................8-12
Table 8-6. Descriptor qword for Transmit (IN) Endpoint TX DMA Packet Buffer ............................................................8-13
Table 8-7. Status qword for Transmit (IN) Endpoint TX DMA Packet Buffer...................................................................8-13
Table 8-8. UDC Endpoints..............................................................................................................................................8-14
Table 8-9. USB Registers...............................................................................................................................................8-15
Table 8-10. EP_OUT Receive Pending Level Register ....................................................................................................8-34
Table 9-1. GPIO Registers ...............................................................................................................................................9-2
Table 10-1. M2M Transfer Example 1............................................................................................................................10-1
Table 10-2. M2M Transfer Example 2............................................................................................................................10-2
Table 10-3. M2M Transfer Example 3............................................................................................................................10-2
Table 10-4. M2M Registers ...........................................................................................................................................10-3
Table 11-1. INTC Registers............................................................................................................................................11-1
Table 12-1. Timer Resolution and SDRAM Refresh Rate ...............................................................................................12-2
Table 12-2. Timer Registers ..........................................................................................................................................12-3
Table 13-1. FCLKIO/GPIO39 Pin Usage Control .............................................................................................................13-1
Table 13-2. BCLKIO/GPIO38 Pin Usage Control.............................................................................................................13-1
Table 13-3. FCLK PLL Generated Clocks........................................................................................................................13-4
Table 13-4. BCLK PLL Generated Clocks .......................................................................................................................13-4
Table 13-5. FCLK PLL Generated Clocks Programming Examples .................................................................................13-4
Table 13-6. BCLK PLL Generated Clocks Programming Examples.................................................................................13-4
Table 13-7. PLL Register Memory Map .........................................................................................................................13-5
Table 13-8. Desired Frequencies and Programming Parameters....................................................................................13-8
Table 13-9. Clocking Requirements...............................................................................................................................13-9
Table 14-1. Register Type Definition..............................................................................................................................14-1
Table 14-2. CX82100 Interface Registers Sorted by Supported Function.......................................................................14-2
Table 14-3. CX82100 Interface Registers Sorted by Address.........................................................................................14-6
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