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CX28395-19 参数 Datasheet PDF下载

CX28395-19图片预览
型号: CX28395-19
PDF下载: 下载PDF文件 查看货源
内容描述: 四核/ X16 /八路T1 / E1 / J1成帧器 [Quad/x16/Octal?T1/E1/J1 Framers]
分类和应用: 电信集成电路
文件页数/大小: 305 页 / 1863 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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CX28394/28395/28398  
3.0 Registers  
Quad/x16/OctalT1/E1/J1 Framers  
3.15 Data Link Registers  
Non-FCS mode passes all message bits that exist between the opening and closing FLAG  
characters through the FIFOs, without generating or checking FCS bits. Non-FCS mode allows  
the processor to generate and check the entire contents of each HDLC frame. Unformatted  
data link modes provide transparent channel access in which every data link bit transmitted is  
supplied by the processor through TDL1 and each bit received is passed to the processor  
through RDL1 [addr 0A8]. Pack8 and Pack6 unformatted mode options select the number of  
bits per byte that are stored in transmit/receive FIFOs, eight or six bits, respectively. The only  
data processing performed during unformatted mode is the alignment of transmitted and  
received data bits with respect to the transmit/receive multiframe.  
00 = FCS  
01 = No FCS  
10 = Pack8  
11 = Pack6  
TDL1_EN  
RDL1_EN  
Transmit Data Link 1 Enable—When enabled, transmitter begins to empty and to format the  
contents of the transmit data link FIFO for output during the selected time slot bits according  
to the selected DL1[1:0] mode. Also enables generation of transmitter data link interrupt  
events.  
0 = disabled  
1 = enable transmit data link  
Receive Data Link 1 Enable—When enabled, receiver begins to format data from the selected  
time slot bits and to fill the receive data link FIFO according to the selected DL1[1:0] mode.  
Also enables generation of receiver data link interrupt events.  
0 = disabled  
1 = enable receive data link  
0A7—RDL #1 FIFO Fill Control (RDL1_FFC)  
7
6
5
4
3
2
1
0
MSG_FILL[1]  
MSG_FILL[0]  
FFC[5]  
FFC[4]  
FFC[3]  
FFC[2]  
FFC[1]  
FFC[0]  
MSG_FILL[1:0]  
Unformatted Message Fill Limit—Applicable only for Pack8 and Pack6 modes, the message  
fill limit selects how many receive FIFO locations [RDL1; addr 0A8] are filled before the  
receive data link generates an RFULL interrupt [ISR2; addr 009] and generates a  
corresponding RDL1 Partial message status word entry. Fill limit thus determines how many  
bytes constitute an unformatted message. Fill limits give the processor an alternative to using  
RNEAR interrupts to signal the end of a received unformatted message. Note the number of  
bits per unformatted message must divide evenly by the number of bits monitored per  
multiframe.  
100054E  
Conexant  
3-77  
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