CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.15 Data Link Registers
3.15 Data Link Registers
Each framer contains two independent Data Link Controllers (DL1, DL2), which are programmed to send and
receive HDLC formatted or unformatted serial data over any combination of bits within a selected time slot. The
serial data channels operate at a multiple of 4 kbps up to the full 64 kbps time slot rate by selecting a
combination of time slot bits from odd, even, or all frames. DL1 and DL2 each contain a 64-byte receive and
64-byte transmit buffer which, function either as programmable length circular buffers or full-length data
FIFOs.
0A4—DL1 Time Slot Enable (DL1_TS)
7
6
5
4
3
2
1
0
DL1_TS[7]
DL1_TS[6]
DL1_TS[5]
DL1_TS[4]
DL1_TS[3]
DL1_TS[2]
DL1_TS[1]
DL1_TS[0]
DL1_TS[7]
DL1_TS[6, 5]
Unchannelized—Test mode only; all time slots selected. Zero for normal operation.
Frame Select—Transmit and receive data link 1 operates on data only during the specified
T1/E1 frames. Frame select options give the processor access to different types of data link
channels as well as overhead channels. Note that overhead bit insertion is performed after
TDL1, so internal transmitter overhead insertion must be bypassed [TFRM; addr 072] before
processor supplied overhead can be output from TDL1.
00 = all frames
01 = even frames only
10 = odd frames only
11 = not valid
DL1_TS[4:0]
Time Slot Word Enable—Transmit and receive data link 1 operates on data only during the
specified time slot. During T1 mode, selecting time slot zero enables data link operation on the
F-bit positions.
DL1_TS[4:0]
00000
00001
|
Time Slot Enable
F-bit (T1) or TS0 (E1)
TS1
|
11110
11111
TS30
TS31
100054E
Conexant
3-75
CONEXANT [ CONEXANT SYSTEMS, INC ]
