3.0 Registers
CX28394/28395/28398
3.15 Data Link Registers
Quad/x16/Octal—T1/E1/J1 Framers
0A5—DL1 Bit Enable (DL1_BIT)
7
6
5
4
3
2
1
0
DL1_BIT[7]
DL1_BIT[6]
DL1_BIT[5]
DL1_BIT[4]
DL1_BIT[3]
DL1_BIT[2]
DL1_BIT[1]
DL1_BIT[0]
DL1_BIT[7:0]
DL1 Bit Select—Works in conjunction with DL1_TS [addr 0A4] to select one or more time
slot bits for data link input and output. Any combination of bits may be enabled by writing the
corresponding DL1_BIT active (high). The LSB enables first bit transmitted or received, and
MSB enables eighth bit transmitted or received. DL1_BIT has no effect when DL1_TS selects
T1 F-bits.
0 = disable data link bit
1 = enable data link bit
0A6—DL1 Control (DL1_CTL)
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
—
—
—
TDL1_RPT
DL1[1]
DL1[0]
TDL1_EN
RDL1_EN
TDL1_RPT
Circular Transmit Buffer Enable—Processor can fill the transmit FIFO [TDL1; addr 0AD]
with up to 64 bytes (Pack6 or Pack8 bits/byte) of unformatted data to be sent repeatedly. While
TDL1_RPT is active high, data written to TDL1 is held until the processor writes an end of
message [TDL1_EOM; addr 0AC]. After TDL1_EOM is written, the transmitter waits for the
beginning of the next output multiframe (based on the selected transmit framing mode) before
sending the first byte of the circular buffer. Subsequent bytes are output in the selected time
slot/overhead bits and will continue to wrap around (recirculate) from the buffer until the
processor writes new buffer data and another TDL1_EOM. This allows the processor to send
multiframe aligned data patterns in ESF, SF, SLC, FAS, MFAS or CAS overhead bits.
0 = normal transmit FIFO
1 = enable circular transmit buffer
DL1[1: 0]
Data Link 1 Mode—Selects either HDLC-formatted (FCS or Non-FCS) transmit and receive
data link message mode or unformatted (Pack8 or Pack6) message mode. During HDLC
modes, the transmit/receive circuits perform zero insertion/removal after each occurrence of 5
consecutive ones contained in the message bits, FLAG (0x7E) character insertion/removal
during idle channel conditions, and ABORT (0xFF) code insertion/detection upon errored
channel conditions. Refer to ITU-T Recommendation Q.921 for complete details of the HDLC
link-layer protocol. FCS mode automatically generates, inserts, and checks the 16-bit Frame
Check Sequence (FCS) without passing FCS bits through transmit and receive FIFOs.
3-76
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
